Patents by Inventor Amit Pabalkar

Amit Pabalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886262
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
  • Patent number: 11137815
    Abstract: Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 5, 2021
    Assignee: NVIDIA Corporation
    Inventor: Amit Pabalkar
  • Patent number: 11106261
    Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 31, 2021
    Assignee: NVIDIA CORPORATION
    Inventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
  • Publication number: 20210255680
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Sau Yan Keith LI, Thomas E. DEWEY, Arthur CHEN, Simon LAI, Amit PABALKAR, Santosh NAYAK
  • Patent number: 10996725
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 4, 2021
    Assignee: NVIDIA Corporation
    Inventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
  • Publication number: 20200142466
    Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 7, 2020
    Inventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
  • Publication number: 20200064894
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Sau Yan Keith LI, Thomas E. DEWEY, Arthur CHEN, Simon LAI, Amit PABALKAR, Santosh NAYAK
  • Publication number: 20190286214
    Abstract: Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventor: Amit Pabalkar