Patents by Inventor Amit S. Sharma
Amit S. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145029Abstract: The present invention discloses a system and method for determination and prioritization of a plurality of secondary target protein. According to the invention, the present invention ensures the abstraction and authentication of possible scientific data for the primary target protein and introduces a statistical analysis of multiple similarity criteria to determine similar proteins in the form of the plurality of secondary target protein for an input query. Furthermore, the identified plurality of secondary target protein is analysed via matrix and multi-relational directed network analysis to prioritize and depict relationships among similarity concepts. Beneficially, the present invention ensures a high level of coverage and precision to descript protein-protein similarity.Type: ApplicationFiled: November 1, 2022Publication date: May 2, 2024Applicant: Innoplexus AGInventors: Om Prakash Sharma, Vinay Chandil, Amit S. Choudhari
-
Publication number: 20240111970Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.Type: ApplicationFiled: December 4, 2023Publication date: April 4, 2024Inventors: John Paul Strachan, Dejan S. Milojicic, Martin Foltin, Sai Rahul Chalamalasetti, Amit S. Sharma
-
Patent number: 11861429Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.Type: GrantFiled: April 30, 2018Date of Patent: January 2, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: John Paul Strachan, Dejan S. Milojicic, Martin Foltin, Sai Rahul Chalamalasetti, Amit S. Sharma
-
Publication number: 20230208612Abstract: Systems and methods are provided for encrypting data in a memristor array. The data may be scrambled by multiplying an input data unit by another data unit, by multiplying each element of a first data unit by a different instance of a second data unit. The process continues until all elements of the first data unit are multiplied by a different instance of the second data unit. The elements of the data units may be represented by resistive values of a memristor array. The result of all of the above multiplication of different instances of the second data unit are a new set of data units. All of the resulting data units are added together by adding the currents associated with values of the memristors representing the resulting data units. The operation may be performed as a finite field computation, with the memristor array.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventor: AMIT S. SHARMA
-
Patent number: 11532356Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: GrantFiled: April 6, 2021Date of Patent: December 20, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
-
Patent number: 11322545Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.Type: GrantFiled: April 27, 2018Date of Patent: May 3, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Martin Foltin
-
Publication number: 20210240945Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.Type: ApplicationFiled: April 30, 2018Publication date: August 5, 2021Applicant: Hewlett Packard Enterprise Development LPInventors: John Paul STRACHAN, Dejan S. MILOJICIC, Martin FOLTIN, Sai Rahul CHALAMALASETTI, Amit S. SHARMA
-
Publication number: 20210225440Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
-
Patent number: 10984860Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: GrantFiled: March 26, 2019Date of Patent: April 20, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
-
Patent number: 10930343Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.Type: GrantFiled: August 21, 2018Date of Patent: February 23, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, Suhas Kumar, Xia Sheng
-
Publication number: 20210036058Abstract: Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.Type: ApplicationFiled: April 27, 2018Publication date: February 4, 2021Inventors: Amit S. Sharma, John Paul Strachan, Martin Foltin
-
Patent number: 10845535Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.Type: GrantFiled: December 10, 2019Date of Patent: November 24, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Marco Fiorentino
-
Publication number: 20200312406Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
-
Publication number: 20200116931Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: Amit S. Sharma, John Paul Strachan, Marco Fiorentino
-
Publication number: 20200066340Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Amit S. Sharma, Suhas Kumar, Xia Sheng
-
Patent number: 10509167Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.Type: GrantFiled: April 23, 2018Date of Patent: December 17, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Marco Fiorentino
-
Publication number: 20190324205Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.Type: ApplicationFiled: April 23, 2018Publication date: October 24, 2019Inventors: Amit S. Sharma, John Paul Strachan, Marco Fiorentino
-
Patent number: 10146619Abstract: According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.Type: GrantFiled: July 31, 2014Date of Patent: December 4, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Naveen Muralimanohar, Erik Ordentlich, Amit S. Sharma
-
Publication number: 20170287540Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.Type: ApplicationFiled: September 25, 2014Publication date: October 5, 2017Inventors: Brent Buchanan, Amit S. Sharma, Gary Gibson, Erik Ordentlich, Naveen Muralimanohar
-
Patent number: 9767901Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.Type: GrantFiled: August 24, 2016Date of Patent: September 19, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, Gary Gibson, Naveen Muralimanohar, Martin Foltin, Greg Astfalk