Patents by Inventor Amitabh Das
Amitabh Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966283Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.Type: GrantFiled: November 30, 2022Date of Patent: April 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Divya Madapusi Srinivas Prasad, Sudhanva Gurumurthi, Yasuko Eckert, Jeffrey Richard Rearick, Sankaranarayanan Gurumurthy, Amitabh Mehra, Shidhartha Das, Alex W. Schaefer, Vikram Ramachandra, Vilas Sridharan
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Patent number: 11562063Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.Type: GrantFiled: December 7, 2020Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Michael Lemay, David M. Durham, Michael E. Kounavis, Barry E. Huntley, Vedvyas Shanbhogue, Jason W. Brandt, Josh Triplett, Gilbert Neiger, Karanvir Grewal, Baiju Patel, Ye Zhuang, Jr-Shian Tsai, Vadim Sukhomlinov, Ravi Sahita, Mingwei Zhang, James C. Farwell, Amitabh Das, Krishna Bhuyan
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Patent number: 11496486Abstract: A data processing system includes technology to enable implicit integrity to be used for digital communications. That technology comprises a hardware processor and an implicit integrity engine (IIE) responsive to the processor. For instance, in response to the data processing system receiving a communication that contains a message, the IIE is to automatically analyze the communication to determine whether the message was sent with implicit integrity. If the message was sent with implicit integrity, the IIE is to automatically use a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message, and to automatically determine whether the message has low entropy, based on results of the pattern matching algorithm and a predetermined entropy threshold. If the message does not have low entropy, the IIE is to automatically determine that the message has been corrupted. Other embodiments are described and claimed.Type: GrantFiled: May 13, 2021Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
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Patent number: 11475145Abstract: A programmable logic device that is interposed between a client device and a database server is provided. The client device may issue read and write queries to the programmable logic device. The programmable logic device may serve as a cache. For read queries, confidential data that is stored locally on the programmable device or retrieved from the database server may be encrypted before sending it back to the client device. Non-confidential data may be left unencrypted and can be sent back to the client device in unencrypted form. The programmable logic device may be partially reconfigured during runtime to update database securities settings without causing unnecessary downtime for the overall system.Type: GrantFiled: December 14, 2018Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Kekai Hu, Amitabh Das
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Publication number: 20210266330Abstract: A data processing system includes technology to enable implicit integrity to be used for digital communications. That technology comprises a hardware processor and an implicit integrity engine (IIE) responsive to the processor. For instance, in response to the data processing system receiving a communication that contains a message, the IIE is to automatically analyze the communication to determine whether the message was sent with implicit integrity. If the message was sent with implicit integrity, the IIE is to automatically use a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message, and to automatically determine whether the message has low entropy, based on results of the pattern matching algorithm and a predetermined entropy threshold. If the message does not have low entropy, the IIE is to automatically determine that the message has been corrupted. Other embodiments are described and claimed.Type: ApplicationFiled: May 13, 2021Publication date: August 26, 2021Inventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
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Patent number: 11082432Abstract: Before sending a message to a destination device, a source device automatically uses a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message. The pattern matching algorithm uses at least one pattern matching test to generate at least one entropy metric for the message. The source device automatically determines whether the message has sufficiently low entropy, based on results of the pattern matching algorithm. In response to a determination that the message does not have sufficiently low entropy, the source device automatically generates integrity metadata for the message and sends the integrity metadata to the destination device. However, in response to a determination that the message has sufficiently low entropy, the source device sends the message to the destination device without sending any integrity metadata for the message to the destination device. Other embodiments are described and claimed.Type: GrantFiled: December 5, 2017Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
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Publication number: 20210117535Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: Michael LEMAY, David M. DURHAM, Michael E. KOUNAVIS, Barry E. HUNTLEY, Vedvyas SHANBHOGUE, Jason W. BRANDT, Josh TRIPLETT, Gilbert NEIGER, Karanvir GREWAL, Baiju PATEL, Ye ZHUANG, Jr-Shian TSAI, Vadim SUKHOMLINOV, Ravi SAHITA, Mingwei ZHANG, James C. FARWELL, Amitabh DAS, Krishna BHUYAN
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Patent number: 10929527Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.Type: GrantFiled: December 20, 2017Date of Patent: February 23, 2021Assignee: INTEL CORPORATIONInventors: Michael Kounavis, David Durham, Sergej Deutsch, Saeedeh Komijani, Amitabh Das
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Patent number: 10860709Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.Type: GrantFiled: June 29, 2018Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Michael Lemay, David M. Durham, Michael E. Kounavis, Barry E. Huntley, Vedvyas Shanbhogue, Jason W. Brandt, Josh Triplett, Gilbert Neiger, Karanvir Grewal, Baiju V. Patel, Ye Zhuang, Jr-Shian Tsai, Vadim Sukhomlinov, Ravi Sahita, Mingwei Zhang, James C. Farwell, Amitabh Das, Krishna Bhuyan
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Publication number: 20200004953Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Michael LEMAY, David M. DURHAM, Michael E. KOUNAVIS, Barry E. HUNTLEY, Vedvyas SHANBHOGUE, Jason W. BRANDT, Josh TRIPLETT, Gilbert NEIGER, Karanvir GREWAL, Baiju V. PATEL, Ye ZHUANG, Jr-Shian TSAI, Vadim SUKHOMLINOV, Ravi SAHITA, Mingwei ZHANG, James C. FARWELL, Amitabh DAS, Krishna BHUYAN
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Patent number: 10339979Abstract: An embodiment includes an apparatus comprising: power supply pins to couple to a power supply; a protection block, including a first transistor, to: (a) determine whether voltage from the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first and second function blocks; and the first function block, coupled to the protection block and the power supply pins, including a second transistor and at least one fuse that corresponds to a security key; wherein the first transistor is at least one of: (a) connected in series with at least one other transistor, and (b) having a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor. Other embodiments are described herein.Type: GrantFiled: June 22, 2015Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Seyed-Abdollah Aftabjahani, Amitabh Das
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Publication number: 20190138739Abstract: A programmable logic device that is interposed between a client device and a database server is provided. The client device may issue read and write queries to the programmable logic device. The programmable logic device may serve as a cache. For read queries, confidential data that is stored locally on the programmable device or retrieved from the database server may be encrypted before sending it back to the client device. Non-confidential data may be left unencrypted and can be sent back to the client device in unencrypted form. The programmable logic device may be partially reconfigured during runtime to update database securities settings without causing unnecessary downtime for the overall system.Type: ApplicationFiled: December 14, 2018Publication date: May 9, 2019Applicant: Intel CorporationInventors: Kekai Hu, Amitabh Das
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Publication number: 20190042734Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.Type: ApplicationFiled: December 20, 2017Publication date: February 7, 2019Inventors: Michael Kounavis, David Durham, Sergej Deutsch, Saeedeh Komijani, Amitabh Das
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Publication number: 20190044954Abstract: Before sending a message to a destination device, a source device automatically uses a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message. The pattern matching algorithm uses at least one pattern matching test to generate at least one entropy metric for the message. The source device automatically determines whether the message has sufficiently low entropy, based on results of the pattern matching algorithm. In response to a determination that the message does not have sufficiently low entropy, the source device automatically generates integrity metadata for the message and sends the integrity metadata to the destination device. However, in response to a determination that the message has sufficiently low entropy, the source device sends the message to the destination device without sending any integrity metadata for the message to the destination device. Other embodiments are described and claimed.Type: ApplicationFiled: December 5, 2017Publication date: February 7, 2019Inventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
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Publication number: 20160372913Abstract: An embodiment includes an apparatus comprising: power supply pins to couple to a power supply; a protection block, including a first transistor, to: (a) determine whether voltage from the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first and second function blocks; and the first function block, coupled to the protection block and the power supply pins, including a second transistor and at least one fuse that corresponds to a security key; wherein the first transistor is at least one of: (a) connected in series with at least one other transistor, and (b) having a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor. Other embodiments are described herein.Type: ApplicationFiled: June 22, 2015Publication date: December 22, 2016Inventors: Seyed-Abdollah Aftabjahani, Amitabh Das
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Patent number: 8188832Abstract: A microchip resistor device is disclosed in which first and second resistive elements are formed on a substrate. The first resistive element has a first resistance value and a positive temperature coefficient of resistance (TCR) over a selected temperature range. The second resistive element has a second resistance value and a negative TCR over the selected temperature range. The first and second resistive elements do not overlap each other. The first and second resistive elements are operatively connected with one or more conductors to provide a current path between the two elements. The product of the first resistance value and the positive temperature coefficient of resistance is substantially equal in magnitude to the product of the second resistance value and the negative temperature coefficient of resistance.Type: GrantFiled: May 5, 2010Date of Patent: May 29, 2012Assignee: State of the Art, Inc.Inventors: Amitabh Das, Robert J. Hufnagel, Christopher R. Grabbe
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Publication number: 20110273263Abstract: A microchip resistor device is disclosed in which first and second resistive elements are formed on a substrate. The first resistive element has a first resistance value and a positive temperature coefficient of resistance (TCR) over a selected temperature range. The second resistive element has a second resistance value and a negative TCR over the selected temperature range. The first and second resistive elements do not overlap each other. The first and second resistive elements are operatively connected with one or more conductors to provide a current path between the two elements. The product of the first resistance value and the positive temperature coefficient of resistance is substantially equal in magnitude to the product of the second resistance value and the negative temperature coefficient of resistance.Type: ApplicationFiled: May 5, 2010Publication date: November 10, 2011Inventors: Amitabh Das, Robert J. Hufnagel, Christopher R. Grabbe
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Patent number: 7852171Abstract: A microchip device is disclosed that combines a signal attenuator and a frequency filter. An embodiment of the device includes an input contact, an output contact, and a ground contact formed on the surface of a substrate. Resistive elements formed on the substrate interconnect the contacts. At least the input contact includes a gap pattern formed therein that is dimensioned and arranged such that the input contact provides a reactive impedance characteristic. The combination of the resistance of the resistive elements and the reactive impedance characteristic of the input contact are selected to provide attenuation and frequency filtering of a high frequency signal input to the microchip device. A method of manufacturing the filter-attenuator microchip device is also described.Type: GrantFiled: March 12, 2008Date of Patent: December 14, 2010Assignee: State of the Art, Inc.Inventors: Amitabh Das, Robert J. Hufnagel
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Publication number: 20090231068Abstract: A microchip device is disclosed that combines a signal attenuator and a frequency filter. An embodiment of the device includes an input contact, an output contact, and a ground contact formed on the surface of a substrate. Resistive elements formed on the substrate interconnect the contacts. At least the input contact includes a gap pattern formed therein that is dimensioned and arranged such that the input contact provides a reactive impedance characteristic. The combination of the resistance of the resistive elements and the reactive impedance characteristic of the input contact are selected to provide attenuation and frequency filtering of a high frequency signal input to the microchip device. A method of manufacturing the filter-attenuator microchip device is also described.Type: ApplicationFiled: March 12, 2008Publication date: September 17, 2009Inventors: Amitabh Das, Robert J. Hufnagel
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Patent number: 6287681Abstract: Wear resistant overlays for use in decorative laminates and laminates prepared therefrom comprising a web of cellulosic fibers having deposited on the surface thereof a layer of mineral pigment composite particles wherein said composite particles comprise mineral pigment particles embedded in a cured carrier material are disclosed. A process for forming an abrasion resistant overlay sheet which comprises forming a web of cellulosic fibers on a papermaking machine and applying a slurry including mineral pigment composite particles to the upper surface of the web on the papermaking machine wherein said mineral pigment composite particles comprise mineral pigment particles embedded in a cured carrier material is also disclosed.Type: GrantFiled: July 20, 1999Date of Patent: September 11, 2001Assignee: The Mead CorporationInventors: Mahendra Mehta, Amitabh Das, John Rourke