Abstract: The present invention relates to an optical fiber having a core extending parallelly along a central axis of the optical fiber, an inner cladding surrounding the core and an outer cladding surrounding the inner cladding. In particular, the core is up-doped with first and second up-dopants and the inner cladding is up-doped with the second up-dopant. Moreover, the outer cladding is un-doped. Further, the optical fiber has an attenuation of less than 0.2 at a wavelength of 1625 nanometres (nm), the attenuation of less than 0.18 at a wavelength of 1550 nm, or the attenuation of less than 0.32 at a wavelength of 1310 nm and a cable cutoff in a range of 1186 nanometres (nm) to 1194 nm.

Abstract: A method for sintering of a glass preform with reduced helium gas consumption and with reduced cost without affecting any optical or other parameter of the fiber obtained from glass preform processed in this way. The method includes a first step to perform dehydration of the glass preform inside a dehydration module, a second step to perform down-feeding of the glass preform inside a sintering furnace, a third step to perform sintering of the glass preform inside the sintering furnace, a fourth step to move the glass preform in upward motion, and a fifth step to perform re-sintering of the glass preform inside the sintering furnace. Also, the glass preform undergoes dehydration for time period in range of about 20 minutes to 120 minutes. Also, dehydration of the glass preform is performed in presence of helium gas.

Abstract: A system to vent a moist gas stream is disclosed. The system includes an enclosure and an electrochemical cell disposed within the enclosure, the electrochemical cell productive of the moist gas stream. A first vent is in fluid communication with the electrochemical cell for venting the moist gas stream to an exterior of the enclosure, and a second vent is in fluid communication with an interior of the enclosure and in thermal communication with the first vent for discharging heated air to the exterior of the enclosure. At least a portion of the discharging heated air is for preventing freezing of the moist gas stream within the first vent.

Abstract: A method for manufacturing an optical fiber having uniform refractive index profile, and substantially reduced macrobending loss and attenuation loss is provided comprising controlling one or more of parameters including concentration of dopant in outer region and inner region of the core region with respect to middle region of the core region of the optical fiber preform, duration of dehydration process step, concentration of chlorine gas to control refractive index of outer region and inner region of the core region for achieving a fiber having substantially uniform refractive index profile, and substantially reduced macrobending loss and attenuation loss.

Abstract: A system to vent a moist gas stream is disclosed. The system includes an enclosure and an electrochemical cell disposed within the enclosure, the electrochemical cell productive of the moist gas stream. A first vent is in fluid communication with the electrochemical cell for venting the moist gas stream to an exterior of the enclosure, and a second vent is in fluid communication with an interior of the enclosure and in thermal communication with the first vent for discharging heated air to the exterior of the enclosure. At least a portion of the discharging heated air is for preventing freezing of the moist gas stream within the first vent.

Abstract: Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: A system for delivering hydrogen to a vehicle is provided which includes a first hydrogen generator coupled to a first compressor. A second hydrogen generator is also provided that produces hydrogen gas at a pressure at least 2 times that produced by said first generator. Coupled to the second hydrogen generator is a second compressor that increases the pressure of the hydrogen gas produces to a desired delivery pressure. A storage vessel is coupled to both first and second compressors to store the hydrogen gas at a desired pressure level prior to dispensing.

Abstract: Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Abstract: An integrated circuit (IC) component of a computer system, intended for use as part of a production version of the system, is provided with a built-in test unit and core function circuitry that are coupled to transfer information over the same I/O buffer circuitry of the component. The test unit is to transfer test information during a test session and to recognize announcement of the test session via an assertion and a deassertion, for predetermined time intervals, of an inter-component signal.