Patents by Inventor Amlan Sen

Amlan Sen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817326
    Abstract: Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 14, 2023
    Assignee: PYXIS CF PTE. LTD.
    Inventors: Amlan Sen, Chian Soon Chua, Qing Feng Guan, Wai Hoe Lee
  • Patent number: 11810797
    Abstract: A wet processing apparatus and an operation method thereof are provided. The wet processing apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a wet processing solution; and a fixing device configured to fix the substrate at the opening of the side wall. The operation method of the wet processing apparatus includes: placing the substrate on an outer side of the side wall and at the position of the opening, and operating the fixing device to fix the substrate; and performing wet processing treatment on the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 7, 2023
    Assignee: PYXIS CF PTE. LTD.
    Inventors: Amlan Sen, Navaneetha Kumaran Baheerathan
  • Patent number: 11552043
    Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP includes dies bonded face down onto an alignment carrier configured with die bond regions. Pre-bond and post bond inspection are performed at the carrier level to ensure accurate bonding of the dies to the carrier.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 10, 2023
    Assignee: PYXIS CF PTE. LTD.
    Inventors: Amlan Sen, Chian Soon Chua, Wai Hoe Lee, Qing Feng Guan
  • Patent number: 11518070
    Abstract: A compression molding machine including a base part; a first mold chase fixed in a position spaced apart from the base part; a second mold chase disposed between the base part and the first mold chase, the second mold chase movable along a movement axis extending perpendicularly between the base part and the first mold chase; and a compression actuation arrangement for moving the second mold chase. The compression actuation arrangement including at least two independent actuating units, each having a first inverted wedge member, a second wedge member, and a drive mechanism. An inclined surface of the first inverted wedge member and an inclined surface of the second wedge member is slidably engaged to each other to convert a motion of the second wedge member along the transmission axis to a motion of the first inverted wedge member along the actuation axis for moving the second mold chase.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 6, 2022
    Assignee: PYXIS CF PTE. LTD.
    Inventor: Amlan Sen
  • Patent number: 11456259
    Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: September 27, 2022
    Assignee: PYXIS CF PTE. LTD.
    Inventor: Amlan Sen
  • Publication number: 20220178044
    Abstract: A plating apparatus and a plating method thereof are provided. The plating apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a plating solution; a fixing device configured to fix the substrate at the opening of the side wall; at least one sealing element disposed around the opening; and a cleaning module coupled to the tank body for cleaning the at least one sealing element. A cleaning method is also provided for cleaning the at least one sealing element with the cleaning module after operation of the plating apparatus.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Amlan SEN, Navaneetha Kumaran BAHEERATHAN
  • Publication number: 20220102189
    Abstract: A die bonding apparatus having: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane, a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported, and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 31, 2022
    Inventors: HWEE SENG CHEW, AMLAN SEN, LI JIANG HUANG, SIEW WEN LEE, QING FENG GUAN, WAI HOE LEE, KIN FEI CHOOI
  • Patent number: 11261535
    Abstract: A plating apparatus and an operation method thereof are provided. The plating apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a plating solution; and a fixing device configured to fix the substrate at the opening of the side wall. The operation method of the plating apparatus includes: placing the substrate on an outer side of the side wall and at the position of the opening, and operating the fixing device to fix the substrate; and performing plating treatment on the substrate.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 1, 2022
    Assignee: PYXIS CF PTE. LTD.
    Inventors: Amlan Sen, Navaneetha Kumaran Baheerathan
  • Publication number: 20220028703
    Abstract: Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Amlan Sen, Chian Soon Chua, QING FENG GUAN, WAI HOE LEE
  • Patent number: 11107716
    Abstract: An automation line for processing a molded panel which is attached, via thermal release adhesive, to a first carrier. The automation line including a release workstation which includes a release unit having a carrier-engagement arrangement movable to engage the first carrier. The carrier-engagement arrangement includes a heating sub-arrangement to thermally contact the first carrier and an attachment sub-arrangement to attach the first carrier to the carrier-engagement arrangement, wherein the carrier-engagement arrangement is operable to heat the intermediate panel assembly to a release temperature of the thermal release adhesive and to separate the first carrier from the molded panel.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 31, 2021
    Assignee: PYXIS CF PTE. LTD.
    Inventor: Amlan Sen
  • Publication number: 20210249290
    Abstract: An automation line for processing a molded panel which is attached, via thermal release adhesive, to a first carrier. The automation line including a release workstation which includes a release unit having a carrier-engagement arrangement movable to engage the first carrier. The carrier-engagement arrangement includes a heating sub-arrangement to thermally contact the first carrier and an attachment sub-arrangement to attach the first carrier to the carrier-engagement arrangement, wherein the carrier-engagement arrangement is operable to heat the intermediate panel assembly to a release temperature of the thermal release adhesive and to separate the first carrier from the molded panel.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventor: AMLAN SEN
  • Publication number: 20210118841
    Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP includes dies bonded face down onto an alignment carrier configured with die bond regions. Pre-bond and post bond inspection are performed at the carrier level to ensure accurate bonding of the dies to the carrier.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Amlan SEN, Chian Soon CHUA, Wai Hoe LEE, Qing Feng GUAN
  • Publication number: 20210111045
    Abstract: A wet processing apparatus and an operation method thereof are provided. The wet processing apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a wet processing solution; and a fixing device configured to fix the substrate at the opening of the side wall. The operation method of the wet processing apparatus includes: placing the substrate on an outer side of the side wall and at the position of the opening, and operating the fixing device to fix the substrate; and performing wet processing treatment on the substrate.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 15, 2021
    Inventors: Amlan SEN, Navaneetha Kumaran BAHEERATHAN
  • Publication number: 20200312780
    Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.
    Type: Application
    Filed: March 10, 2020
    Publication date: October 1, 2020
    Inventor: Amlan Sen
  • Publication number: 20200307037
    Abstract: A compression molding machine including a base part; a first mold chase fixed in a position spaced apart from the base part; a second mold chase disposed between the base part and the first mold chase, the second mold chase movable along a movement axis extending perpendicularly between the base part and the first mold chase; and a compression actuation arrangement for moving the second mold chase. The compression actuation arrangement including at least two independent actuating units, each having a first inverted wedge member, a second wedge member, and a drive mechanism. An inclined surface of the first inverted wedge member and an inclined surface of the second wedge member is slidably engaged to each other to convert a motion of the second wedge member along the transmission axis to a motion of the first inverted wedge member along the actuation axis for moving the second mold chase.
    Type: Application
    Filed: March 24, 2020
    Publication date: October 1, 2020
    Inventor: AMLAN SEN
  • Publication number: 20200299854
    Abstract: A plating apparatus and an operation method thereof are provided. The plating apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a plating solution; and a fixing device configured to fix the substrate at the opening of the side wall. The operation method of the plating apparatus includes: placing the substrate on an outer side of the side wall and at the position of the opening, and operating the fixing device to fix the substrate; and performing plating treatment on the substrate.
    Type: Application
    Filed: October 18, 2019
    Publication date: September 24, 2020
    Inventors: Amlan SEN, Navaneetha Kumaran BAHEERATHAN
  • Publication number: 20200083193
    Abstract: An apparatus and method for semiconductor device (such as semiconductor die or die) bonding. The apparatus has a bonding assembly with a bonding head having a bonding tool for holding a semiconductor device; and a bonding head actuation mechanism for actuating the bonding tool horizontally planarly to align the semiconductor device relative to a bonding location of a substrate while the semiconductor device remains above the bonding location. The bonding assembly has a bonding assembly actuator for actuating the bonding head vertically to pick the semiconductor device and to bond the semiconductor device at the bonding location. The apparatus has a vision assembly with alignment cameras for capturing reference views of the semiconductor device and bonding location for aligning the semiconductor device relative to the bonding location, and a vision assembly actuation mechanism for actuating the alignment cameras to position the alignment cameras between the bonding tool and bonding location.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 12, 2020
    Inventor: Amlan SEN
  • Publication number: 20150348895
    Abstract: A method of forming a substrate (10) for semiconductor packaging and a substrate (10) for semiconductor packaging are provided. The method includes providing a carrier (12) and forming a plurality of external pads (14) on the carrier (12), the external pads (14) formed on the carrier (12) defining a first conductive layer. A molding operation is performed to form a first insulating layer (20) on the carrier (12) with a molding compound (22). The first conductive layer is embedded in the first insulating layer (20). One or more of a plurality of bond pads (30), a plurality of conductive traces (32) and a plurality of microvias (56) are formed on the first conductive layer, the one or more of the bond pads (30), the conductive traces (32) and the microvias (56) formed on the first conductive layer defining a second conductive layer.
    Type: Application
    Filed: January 21, 2014
    Publication date: December 3, 2015
    Inventors: Amlan SEN, Shoa-Siong Raymond LIM
  • Patent number: 9120169
    Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: September 1, 2015
    Assignee: ORION SYSTEMS INTEGRATION PTE LTD
    Inventors: Hwee Seng Chew, Chee Kian Ong, Kian Hock Lim, Amlan Sen, Shoa Siong Lim
  • Patent number: 9082775
    Abstract: The present invention describes two systems (100, 300) for encapsulation of semiconductor dies. Both systems (100, 300) involve attaching an encapsulation spacer (102, 302, 302a, 302b) having one or more apertures (104, 304) on an associated substrate (150) so that a group of chips is located within the aperture (104, 304). The first system (100) involves dispensing encapsulant (103) directly into an aperture. The second system (300) involves attaching an encapsulant delivery layer (350, 351) onto the encapsulation spacer and discharging encapsulant into an aperture via a recessed gate (308).
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: July 14, 2015
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Amlan Sen, Chin Guan Khaw