Abstract: A brace for a part of a body includes a first conductive fiber associated with a first polarity, and a second conductive fiber associated with a second polarity different from the first polarity. The second fiber is woven together with the first fiber and insulated from the first fiber. The brace also includes a selectively electrically activated cross-linking agent between the first and second fibers. The agent is constructed to cross-link in a first active mode when the first and second fibers are electrified and is constructed to not cross-link in a second inactive mode when the first and second fibers are not electrified. The brace surrounds a body part, such as a knee or neck. The agent can include an ER fluid and/or EAP. A brace system includes a selectively electrically activated brace for the part of the body.

Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

Abstract: A brace for a part of a body includes a first conductive fiber associated with a first polarity, and a second conductive fiber associated with a second polarity different from the first polarity. The second fiber is woven together with the first fiber and insulated from the first fiber. The brace also includes a selectively electrically activated cross-linking agent between the first and second fibers. The agent is constructed to cross-link in a first active mode when the first and second fibers are electrified and is constructed to not cross-link in a second inactive mode when the first and second fibers are not electrified. The brace surrounds a body part, such as a knee or neck. The agent can include an ER fluid and/or EAP. A brace system includes a selectively electrically activated brace for the part of the body.

Abstract: A brace for a part of a body includes a first conductive fiber associated with a first polarity, and a second conductive fiber associated with a second polarity different from the first polarity. The second fiber is woven together with the first fiber and insulated from the first fiber. The brace also includes a selectively electrically activated cross-linking agent between the first and second fibers. The agent is constructed to cross-link in a first active mode when the first and second fibers are electrified and is constructed to not cross-link in a second inactive mode when the first and second fibers are not electrified. The brace surrounds a body part, such as a knee or neck. The agent can include an ER fluid and/or EAP. A brace system includes a selectively electrically activated brace for the part of the body.

Abstract: Method and apparatus for performing table lookup are disclosed. In one embodiment, the method includes providing a lookup table, where the lookup table includes a plurality of translation modes and each translation mode includes a corresponding translation table tree supporting a plurality of page sizes. The method further includes receiving a search request from a requester, determining a translation table tree for conducting the search request, determining a lookup sequence based on the translation table tree, generating a search output using the lookup sequence, and transmitting the search output to the requester. The plurality of translation modes includes a first set of page sizes for 32-bit operating system software and a second set of page sizes for 64-bit operating system software. The plurality of page sizes includes non-global pages, global pages, and both non-global and global pages.

Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

Abstract: A brace for a part of a body includes a first conductive fiber associated with a first polarity, and a second conductive fiber associated with a second polarity different from the first polarity. The second fiber is woven together with the first fiber and insulated from the first fiber. The brace also includes a selectively electrically activated cross-linking agent between the first and second fibers. The agent is constructed to cross-link in a first active mode when the first and second fibers are electrified and is constructed to not cross-link in a second inactive mode when the first and second fibers are not electrified. The brace surrounds a body part, such as a knee or neck. The agent can include an ER fluid and/or EAP. A brace system includes a selectively electrically activated brace for the part of the body.

Abstract: Accordingly, a prefetch instruction mechanism is desired for implementing a prefetch instruction which is non-faulting, non-blocking, and non-modifying of architectural register state. Advantageously, a prefetch mechanism described herein is provided largely without the addition of substantial complexity to a load execution unit. In one embodiment, the non-faulting attribute of the prefetch mechanism is provided though use of the vector decode supplied Op sequence that activates an alternate exception handler. The non-modifying of architectural register state attribute is provided (in an exemplary embodiment) by first decoding a PREFETCH instruction to an Op sequence targeting a scratch register wherein the scratch register has scope limited to the Op sequence corresponding to the PREFETCH instruction.

Abstract: A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit.

Abstract: In a data processing system, a circuit for providing an even bus clock signal, EVENBCLK, when the leading edges of the bus clock signal BCLK and a processor clock signal PCLK are coincident includes a phase-locked loop unit and a coincidence unit. The phase-locked loop unit provides PCLK signals that have a frequency Nx the frequency of the BCLK signals, where N can have an integer or a half integer value. The phase-locked loop unit includes a divide-by-M unit, where M=2N, that receives the PCLK signal at an input terminal and applies an output signal, PCLK/M, to the phase detector unit of the phase-locked loop unit. The operation of the phase-locked loop results in the BCLK signal and the PCLK/M signal having an established phase relationship. The PCLK signal and the PCLK/M signal are applied to the coincidence unit, the simultaneous application of the two signals resulting in the coincidence unit providing the EVENBCLK signals.

Abstract: A superscalar processor includes a central scheduler for multiple execution units. The scheduler presumes operations issued to a particular execution unit all have the same latency, e.g., one clock cycle, even though some of the operations have longer latencies, e.g., two clock cycles. The execution unit that executes the operations having with longer than expected latencies, includes scheduling circuitry that holds up particular operation pipelines when operands required for the pipelines will not be valid when the scheduler presumes. Accordingly, the design of the scheduler can be simplified and can accommodate longer latency operations without being significantly redesigned for the longer latency operations.

Abstract: A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.

Abstract: Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies.

Abstract: A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.

Abstract: A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array.

Abstract: A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.

Abstract: An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios that includes whole integers and half integers. The even bus clock circuit includes a delay element for receiving the bus clock and generating a delayed bus clock, a first flip-flop for receiving the processor clock at a data input and receiving the delayed bus clock at a clock input, and a second flip-flop for receiving a data output of the first flip-flop at a data input, receiving the processor clock at a clock input and generating a data output that is coupled to an asynchronous reset input of the first flip-flop. The logic pulses are generated at the data output of the first flip-flop and have a pulse width of substantially the same duration as a single cycle of the processor clock.

Abstract: A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit.

Abstract: A processing system includes sequential entries for storing operations of different types and a scan chain which can identify an operation of a first type which follows after an operation of a second type. The first and second types can be identical so that the scan chain identifies the second operation of a particular type in the sequence. The scan chain includes single-entry "generate", "propagate", "kill", and "only" terms which control a scan bit. Conceptually, if the "only" term is not asserted, an entry of the second type generates the scan bit and asserts the "only" term. After the "only" term is asserted, further generation of the scan bit is inhibited. Each entry either propagates the scan bit to the next entry or if the entry is of the first type, kills the scan bit and identifies itself as the selected entry. Look-ahead logic determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries.

Abstract: A processor which includes tags indicating memory addresses for instructions advancing through pipeline stages of the processor and which includes an instruction decoder having a store target address buffer allows a self-modifying code handling system to detect store operations writing into the instruction stream and trigger a self-modifying code fault. In one embodiment of a seIf-modifying code handling system, a store pipe is coupled to a data cache to commit results of a store operation to a memory subsystem. The store pipe supplies a store operation target address indication on commitment of a store operation result. A scheduler includes ordered Op entries for Ops decoded from instructions and includes corresponding first address tags covering memory addresses for the instructions.