Patents by Inventor Amos Fenigstein
Amos Fenigstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7754559Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.Type: GrantFiled: March 19, 2008Date of Patent: July 13, 2010Assignee: Tower Semiconductor Ltd.Inventors: Efraim Aloni, Yakov Roizin, Alexey Heiman, Michael Lisiansky, Amos Fenigstein, Myriam Buchbinder
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Patent number: 7678603Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a curved (e.g., parabolic) surface extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes a lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.Type: GrantFiled: February 26, 2008Date of Patent: March 16, 2010Assignee: Tower Semiconductor Ltd.Inventors: Hai Reznik, Amos Fenigstein, Doron Amihood, David Choen
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Patent number: 7671396Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: GrantFiled: January 4, 2006Date of Patent: March 2, 2010Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Asaf Lahav, Ira Naot, Yakov Roizin
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Patent number: 7608837Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.Type: GrantFiled: November 24, 2006Date of Patent: October 27, 2009Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein, Avi Strum, Alexei Heiman, Doron Pardess
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Publication number: 20090261235Abstract: A CMOS image sensor in which each pixel includes a conventional pinned diode (photodiode), a Wide Dynamic Range (WDR) detection (e.g., a simplified time-to-saturation (TTS)) circuit, a correlated double sampling (CDS) circuit, and a single output chain that is shared by both the CDS and WDR circuits. The pinned diode is used in the conversion of photons into charge in each pixel. In one embodiment, light received by the photodiode is processed using a TTS operation during the CDS integration phase, and the resulting TTS output signal is used to determine whether the photodiode is saturated. When the photodiode is saturated, the TTS output signal is processed to determine the amount of light received by the photodiode. When the photodiode is not saturated, the amount of light received by the photodiode is determined using signals generated by the readout phase of the CDS operation.Type: ApplicationFiled: April 15, 2009Publication date: October 22, 2009Applicant: Tower Semiconductor Ltd.Inventors: Assaf Lahav, Amos Fenigstein
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Publication number: 20090239351Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: TOWER SEMICONDUCTOR LTD.Inventors: Efraim Aloni, Yakov Roizin, Alexey Helman, Michael Lisiansky, Amos Fenigstein, Myriam Buchbinder
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Publication number: 20090181530Abstract: A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Applicant: Tower Semiconductor Ltd.Inventors: Michael Lisiansky, Yakov Roizin, Alexey Heiman, Amos Fenigstein
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Publication number: 20090181491Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.Type: ApplicationFiled: February 20, 2009Publication date: July 16, 2009Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein, Avi Strum, Alexey Heiman, Doron Pardess
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Patent number: 7482233Abstract: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage nodes that is capable of storing electrical charge (e.g., silicon-nitride with traps or oxide with silicon nanocrystals). The source/drain regions of the NVM cells omit lightly-doped drains (which are used in the CMOS FETs), and the NVM cells are formed with thinner sidewall oxide layers than the CMOS FETs to facilitate programming/erasing operations. A production method includes a modified CMOS process flow where the CMOS FET gate structures receive different source/drain diffusions and oxides than the NVM gate structures, but both receive substantially identical sidewall spacers, which are used as charge storage structures in the NVM cells.Type: GrantFiled: May 24, 2007Date of Patent: January 27, 2009Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein
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Patent number: 7400538Abstract: The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected, the erase pulse magnitude is incrementally increased to compensate for the increasing parasitic electrons. When a predetermined maximum drain voltage is reached, the negative gate refresh voltage is applied to refresh the ONO structure, and the drain voltage is reset to an initial state. A novel NROM cell uses a P+ doped polysilicon gate or Top Oxide produced with a high-k dielectric (Alumina) to facilitate blocking the injection of gate electrons, and the Bottom Oxide thickness is selectively thinned to increase hole injection.Type: GrantFiled: October 5, 2006Date of Patent: July 15, 2008Assignee: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Yakov Roizin, Alexey Heiman, Amos Fenigstein
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Publication number: 20080160689Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Applicant: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Assaf Lahav, Ira Naot, Yakov Roizin
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Publication number: 20080145965Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a curved (e.g., parabolic) surface extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes a lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.Type: ApplicationFiled: February 26, 2008Publication date: June 19, 2008Applicant: Tower Semiconductor Ltd.Inventors: Hai Reznik, Amos Fenigstein, Doron Amihood, David Cohen
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Publication number: 20080121808Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.Type: ApplicationFiled: November 24, 2006Publication date: May 29, 2008Applicant: TOWER SEMICONDUCTOR LTD.Inventors: Yakov Roizin, Amos Fenigstein, Avi Strum, Alexei Heiman, Doron Pardess
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Patent number: 7358583Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a curved (e.g., parabolic) surface extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes a lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.Type: GrantFiled: February 24, 2006Date of Patent: April 15, 2008Assignee: Tower Semiconductor Ltd.Inventors: Hai Reznik, Amos Fenigstein, Doron Amihood, David Cohen
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Publication number: 20080084764Abstract: The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected, the erase pulse magnitude is incrementally increased to compensate for the increasing parasitic electrons. When a predetermined maximum drain voltage is reached, the negative gate refresh voltage is applied to refresh the ONO structure, and the drain voltage is reset to an initial state. A novel NROM cell uses a P+ doped polysilicon gate or Top Oxide produced with a high-k dielectric (Alumina) to facilitate blocking the injection of gate electrons, and the Bottom Oxide thickness is selectively thinned to increase hole injection.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Applicant: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Yakov Roizin, Alexey Heiman, Amos Fenigstein
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Publication number: 20070224751Abstract: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage nodes that is capable of storing electrical charge (e.g., silicon-nitride with traps or oxide with silicon nanocrystals). The source/drain regions of the NVM cells omit lightly-doped drains (which are used in the CMOS FETs), and the NVM cells are formed with thinner sidewall oxide layers than the CMOS FETs to facilitate programming/erasing operations. A production method includes a modified CMOS process flow where the CMOS FET gate structures receive different source/drain diffusions and oxides than the NVM gate structures, but both receive substantially identical sidewall spacers, which are used as charge storage structures in the NVM cells.Type: ApplicationFiled: May 24, 2007Publication date: September 27, 2007Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein
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Publication number: 20070200054Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a curved (e.g., parabolic) surface extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes a lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Applicant: Tower Semiconductor Ltd.Inventors: Hai Reznik, Amos Fenigstein, Doron Amihood, David Cohen
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Publication number: 20070200055Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a cone-like surface (e.g., having a tapered roundish or polygonal cross-section) extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes an optional lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Applicant: Tower Semiconductor Ltd.Inventors: Hai Reznik, Amos Fenigstein, Doron Amihood, David Cohen
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Publication number: 20070166912Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: ApplicationFiled: January 4, 2006Publication date: July 19, 2007Applicant: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Asaf Lahav, Ira Naot, Yakov Roizin
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Patent number: 7227234Abstract: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage nodes that is capable of storing electrical charge (e.g., silicon-nitride with traps or oxide with silicon nanocrystals). The source/drain regions of the NVM cells omit lightly-doped drains (which are used in the CMOS FETs), and the NVM cells are formed with thinner sidewall oxide layers than the CMOS FETs to facilitate programming/erasing operations. A production method includes a modified CMOS process flow where the CMOS FET gate structures receive different source/drain diffusions and oxides than the NVM gate structures, but both receive substantially identical sidewall spacers, which are used as charge storage structures in the NVM cells.Type: GrantFiled: April 11, 2005Date of Patent: June 5, 2007Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein