Abstract: A design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example, bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. The connectivity of this physical data base file is checked by first generating a circuit level netlist file for the entire option, and then comparing the circuit level netlist with the physical data base file. In generating the circuit level netlist file, information is obtained from the logic netlist file, as well as from some of the other files created in the design-layout sequence. In addition, basic information from which the circuit level netlist is constructed is obtained from a skeleton file library and a subcircuit library.

Abstract: A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root.