Patents by Inventor An-Cheng Chen
An-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170339Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.Type: ApplicationFiled: March 2, 2023Publication date: May 23, 2024Inventors: Te-Chih Hsiung, Yun-Hua Chen, Yang-Cheng Wu, Sheng-Hsun Fu, Wen-Kuo Hsieh, Chih-Yuan Ting, Huan-Just Lin, Bing-Sian Wu, Yi-Hsuan Chiu
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Publication number: 20240170337Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Kuan-Ting PAN, Jung-Hung CHANG, Lo-Heng CHANG, Chien Ning YAO
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Publication number: 20240170709Abstract: A motion synchronized multi-tier pallet rack and a battery formation apparatus are provided. The pallet rack includes a fixation rack, two movable frames, and two actuators. The movable frames are coupled to two corresponding sides of the fixation rack and each includes telescopic arms, a motor, and a drive rod. The actuators are disposed on other the two corresponding sides of the fixation rack to drive the movable frames to move toward or away from each other. The telescopic arms are kinematically connected to the motor through the drive rod to extend from or retract into the movable frame. The battery formation apparatus includes a motion synchronized multi-tier pallet rack, a conveyor module, a formation cabinet, and a controller. The conveyor module carries a battery module. The controller controls the pallet rack to obtain the battery module from the conveyor module and place the battery module in the formation cabinet.Type: ApplicationFiled: September 27, 2023Publication date: May 23, 2024Applicant: CHROMA ATE INC.Inventors: Ming-Cheng Huang, Jiun-Ren Chen, Chao-Cheng Wu, Yi-Sheng Hsu
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Publication number: 20240170225Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
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Publication number: 20240170556Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.Type: ApplicationFiled: February 20, 2023Publication date: May 23, 2024Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
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Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
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Publication number: 20240169693Abstract: An accuracy measurement kit is provided and includes a marker, at least one light beam device, an image capture device, and a processing device. The marker is disposed on an autonomous mobile vehicle, and at least partially includes a reference pattern. The light beam device is configured to emit a light beam to the autonomous mobile vehicle located at a predetermined position so as to form a light spot on the marker. The processing device is configured to capture the light spot the marker on the autonomous mobile vehicle for generating a to-be-analyzed image. The processing device is configured to obtain an offset of the autonomous mobile vehicle in an X-axis direction and a Y-axis direction by calculating images of the to-be-analyzed image corresponding to the reference pattern and the light spot.Type: ApplicationFiled: February 6, 2023Publication date: May 23, 2024Inventors: PO-CHENG CHEN, KAO-PIN LIN, LIANG-CHIN WANG
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Publication number: 20240168484Abstract: An accuracy measurement method of an autonomous mobile vehicle, a calculating device, and an autonomous mobile vehicle are provided. The accuracy measurement method includes a distance calculating step, a regression center calculating step, and an average calculating step. The distance calculating step includes a controlling step, a light beam emitting step, an image capturing step, an image analyzing step, and a converting step. The regression center calculating step is performed after the distance calculating step is repeatedly performed by at least two times. The accuracy measurement method is performed to obtain an X-axis offset in an X-axis direction, a Y-axis offset in a Y-axis direction, and an angle deflection of an autonomous mobile vehicle.Type: ApplicationFiled: February 6, 2023Publication date: May 23, 2024Inventors: PO-CHENG CHEN, KAO-PIN LIN, LIANG-CHIN WANG
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Publication number: 20240170536Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.Type: ApplicationFiled: January 29, 2024Publication date: May 23, 2024Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Chi On Chui
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Publication number: 20240169376Abstract: An approach is disclosed that receives an incoming data record, the data record including a number of data fields. The approach determines a current Real-Time Resources Score (RTRS). The RTRS being a forecast of the information handling system's ability to handle incoming data transmissions. When the RTRS is lower than a current data accumulation rate, a subset of the data record is sent based on field priorities. The approach assigns priorities to each of the data fields included in the data record based on a priority assessment of the respective data fields. The approach then sends, to a data receiver, a subset of the plurality of data fields based on the assigned priority.Type: ApplicationFiled: November 23, 2022Publication date: May 23, 2024Inventors: LING MA, Cheng Fang Wang, Jing Yan ZZ Zhang, Bing Qian, Wen Wen Guo, Bo Chen Zhu
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Patent number: 11988761Abstract: The present disclosure provides an information transmission method and device, a node, a server and a computer-readable storage medium. The method includes: determining, by a transmitting node, a reference signal for positioning and transmitting configuration information of the reference signal for positioning to a positioning server, with the reference signal for positioning at least including a Positioning Reference Signal (PRS); and transmitting, by the transmitting node, the reference signal according to the configuration information.Type: GrantFiled: April 9, 2020Date of Patent: May 21, 2024Assignee: ZTE CORPORATIONInventors: Cheng Bi, Shijun Chen, Chuangxin Jiang
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Patent number: 11990477Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.Type: GrantFiled: September 24, 2020Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
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Patent number: 11986698Abstract: A method for determining golf shot characteristics includes detecting, in imaging data captured by an imager, a signature of a golf shot launched from a first launch area, a field of view of the imager including one of the first launch area and an area adjacent to the first launch area, and determining, from the imaging data, first golf shot characteristics, the first shot characteristics including a first launch location and a first launch time in combination with determining whether the first launch location and the first launch time correspond to a second launch location and a second launch time for second golf shot characteristics determined from sensor data captured by a further sensor arrangement and when no correspondence is found between the first and second launch locations and the first and second launch times, transmitting the first shot characteristics to a display at the first launch location.Type: GrantFiled: August 17, 2022Date of Patent: May 21, 2024Assignee: TRACKMAN A/SInventors: Fredrik Tuxen, Cheng Chen, Mathias Strandgaard
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Patent number: 11989046Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: February 6, 2023Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Patent number: 11990488Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.Type: GrantFiled: March 12, 2021Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
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Patent number: 11990545Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: GrantFiled: October 19, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
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Publication number: 20240156405Abstract: A smart wearable device has a signal calibration function executed by a signal calibration method and applied to a finger, a limb and/or a neck of a user. The smart wearable device includes at least one physiological signal detector, at least one pressure detector and an operation processor. The at least one physiological signal detector is adapted to abut against a detection area of the user for detecting a physiological signal. The at least one pressure detector is disposed around the at least one physiological signal detector and adapted to detect a pressure value of the detection area. The operation processor is electrically connected with the at least one physiological signal detector and the at least one pressure detector. The operation processor is adapted to optimize the physiological signal when the pressure value exceeds a predefined pressure threshold.Type: ApplicationFiled: January 12, 2024Publication date: May 16, 2024Applicant: PixArt Imaging Inc.Inventors: Yung-Chang Lin, Jian-Cheng Liao, Chun-Chih Chen, Sen-Huang Huang, Yen-Min Chang
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Patent number: D1027927Type: GrantFiled: December 6, 2023Date of Patent: May 21, 2024Inventors: Wenhong Ma, Lei Luo, Hui Xia, Cheng Chen