Patents by Inventor An-Chi Wei

An-Chi Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240174784
    Abstract: The present invention relates to a polymer latex composition, to a method for the preparation of such polymer latex composition, to a compounded latex composition comprising said polymer latex composition, to the use of said polymer latex composition, to a method for making dip-molded articles, to a method for the production of a continuous elastomeric film and for making an elastomeric article, to a method for repairing or reforming an elastomeric film or an article and to articles made by using said polymer latex composition.
    Type: Application
    Filed: March 29, 2022
    Publication date: May 30, 2024
    Applicant: Synthomer Sdn. Bhd.
    Inventors: Zhenli Wei, Yi-Fan Goh, Chi Hoong Chan
  • Patent number: 11996037
    Abstract: A scan-type display apparatus includes an LED array and a data driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The data driver includes multiple data driving circuits, each of which includes a current driver and a detector. The current driver has an output terminal connected to the data line corresponding to the data driving circuit, and outputs one of a drive current and a clamp voltage at the output terminal of the current driver based on a pulse width control signal. The detector is connected to the current driver, and generates a detection signal that indicates whether any one of the LEDs connected to the data line corresponding to the data driving circuit is short circuited based on a detection timing signal and a feed-in voltage related to a voltage at the output terminal of the current driver.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: May 28, 2024
    Assignee: MACROBLOCK, INC.
    Inventors: Chi-Min Hsieh, Che-Wei Chang, Chen-Yuan Kuo, Wei-Hsiang Cheng
  • Patent number: 11995390
    Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
  • Publication number: 20240166784
    Abstract: The present invention relates to a polymer latex composition, to a method for the preparation of such a polymer latex composition, to the use of said polymer latex composition for the production of elastomeric articles, to a compounded latex composition comprising said polymer latex composition, to a method for making dip-molded articles, to a method for making elastomeric articles and to articles made by using said polymer latex composition.
    Type: Application
    Filed: March 8, 2022
    Publication date: May 23, 2024
    Applicant: Synthomer Sdn. Bhd.
    Inventors: Zhenli Wei, Yi-Fan Goh, Chi Hoong Chan
  • Publication number: 20240159269
    Abstract: A rotary bearing assembly is disclosed and includes an input shaft, an inner-ring component, an outer-ring component and a load element. The input shaft is configured to combine a rotating shaft of a motor to provide a power input. The inner-ring component includes a gear set, wherein the inner-ring component is sleeved on the input shaft through the gear set and driven by the input shaft. The outer-ring component is sleeved on the inner-ring component through a load element and engaged with the gear set, wherein when the gear set is driven by the input shaft to drive the inner-ring component, the gear set drives the outer-ring component, and the inner-ring component and the outer-ring component are rotated relatively, wherein one of the inner-ring component and the outer-ring component is served to provide a power output, and a rotational speed difference is between the power input and the power output.
    Type: Application
    Filed: August 8, 2023
    Publication date: May 16, 2024
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Hsien-Lung Tsai, Wei-Ying Chu, Chin-Hsiang Chen
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Publication number: 20240156060
    Abstract: A pet collar structure includes a collar body and an elastic connecting member. The collar body includes beads, a first magnetic fastener and a second magnetic fastener. The first magnetic fastener and second magnetic fastener are detachably magnetically attracted to each other. The elastic connecting member includes a first sleeve portion and a second sleeve portion. The first sleeve portion sleeves the collar body and is positioned neighboring to the first magnetic fastener. The second sleeve portion sleeves the collar body and is positioned neighboring to the second magnetic fastener. With the coordination of the first magnetic fastener, the second magnetic fastener and the elastic connecting member, the collar body is worn on a neck of a pet. When the pet runs, scratches or shakes, with the elastic extension and elastic retraction of the elastic connecting member, the collar body is kept from falling off, hence achieving wearing stability.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 16, 2024
    Inventor: CHI-WEI LIN
  • Patent number: 11983479
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Publication number: 20240153823
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20240152057
    Abstract: The invention relates to an apparatus and a method for characterizing a microlithographic mask. According to one aspect, an apparatus according to the invention comprises at least one light source which emits coherent light, an illumination optical unit which produces a diffraction-limited light spot on the mask from the coherent light of the at least one light source, a scanning device, by use of which it is possible to implement a scanning movement of the diffraction-limited light spot relative to the mask, a sensor unit, and an evaluation unit for evaluating the light that is incident on the sensor unit and has come from the mask, an output coupling element for coupling out a portion of the coherent light emitted by the at least one light source, and an intensity sensor for capturing the intensity of this output coupled portion.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Johannes Ruoff, Heiko Feldmann, Ulrich Matejka, Thomas Thaler, Sascha Perlitz, Shao-Chi Wei, Joerg Frederik Blumrich, Markus Deguenther
  • Patent number: 11978782
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
  • Publication number: 20240142270
    Abstract: A dynamic calibration method for heterogeneous sensors includes: sensing dynamic objects by a first sensor to generate first sensing data; sensing the dynamic objects by a second sensor to generate second sensing data; performing feature matching between the first sensing data and the second sensing data to determine first valid data and second valid data, and identifying a tracked object from the dynamic objects based on the first valid data and the second valid data; performing feature comparison between the first valid data and the second valid data corresponding to the tracked object to calculate data errors between the first sensor and the second sensor; and calculating a calibration parameter based on the first valid data and the second valid data when the number of the data errors exceeds an error threshold, and adjusting the first sensing data and the second sensing data based on the calibration parameter.
    Type: Application
    Filed: January 12, 2023
    Publication date: May 2, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Wei Chen, Chi-Hung Wang, Che-Jui Chang
  • Publication number: 20240146501
    Abstract: A method of monitoring a clock signal of a server is provided. The server includes a phase-locked loop (PLL), a baseboard management controller (BMC), and a light emitting unit. The method includes steps of: A) the server executing a time synchronization service to obtain a synchronization mode that the PLL is operating in, where the synchronization mode is one of a free-run mode, a locked mode, and a holdover mode; B) the server updating the synchronization mode to the BMC when executing the time synchronization service; and C) the BMC storing the synchronization mode and controlling the light emitting unit to display in one of a plurality of displaying manners that corresponds to the synchronization mode.
    Type: Application
    Filed: July 10, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Yuan Chen, Po-Wei Chang, Chi-Hua Li
  • Patent number: 11969450
    Abstract: Disclosed herein are methods for improving gastrointestinal barrier function, alleviating a gastrointestinal barrier dysfunction-associated disorder, and inhibiting growth of enteric pathogenic bacteria using a composition containing Lactobacillus rhamnosus MP108, Bifidobacterium longum subsp. infantis BLI-02, and Bifidobacterium animalis subsp. lactis BB-115, which are deposited at the China General Microbiological Culture Collection Center (CGMCC) respectively under accession numbers CGMCC 21225, CGMCC 15212, and CGMCC 21840. A number ratio of Lactobacillus rhamnosus MP108, Bifidobacterium longum subsp. infantis BLI-02, and Bifidobacterium animalis subsp. lactis BB-115 ranges from 1:0.2:0.67 to 1:9:9.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 30, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Jui-Fen Chen, Yi-Wei Kuo, Chi-Huei Lin
  • Patent number: 11970342
    Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: April 30, 2024
    Assignee: CHROMA ATE INC.
    Inventors: Chien-Ming Chen, Jui-Hsiung Chen, Chi-Wei Wang
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240133018
    Abstract: A metal mask includes: a mask body having two opposite first side edges along a first direction and two opposite second side edges along a second direction, and each of the first side edges having a first length. The mask body includes an open slot region, two first fixing regions, and two first clamping regions, where the two first fixing regions are positioned on two opposite sides of the open slot region, respectively, and each of the first clamping regions is positioned between each of the first fixing regions and each of the first side edges. A first gap is formed in each of the first side edges, the first gap has a first opening length in the first direction, and a ratio of the first opening length to the first length being between 0.2 and 0.8. The metal mask may improve the problem of wrinkles.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 25, 2024
    Inventors: YunPei Yang, Chi-Wei Lin
  • Publication number: 20240134691
    Abstract: A system allocates scratchpad memory (SPM) to heterogeneous devices for neural network computing. The system executes the operations of a global optimization manager. The global optimization manager receives compilation states from compilers, which compile corresponding subgraphs of a neural network model into corresponding subcommands that run on the heterogeneous devices. The global optimization manager unifies records of a same object across different ones of the compilation states, and allocates the SPM to the subgraphs according to the unified records of the compilation states.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventor: Chi-Wei Wang