Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: A method includes receiving a plurality of sets of sensor data associated with a processing chamber of a substrate processing system. Each of the plurality of sets of sensor data comprises a corresponding sensor value of the processing chamber mapped to a corresponding spacing value of the processing chamber. The method further includes providing the plurality of sets of sensor data as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of a health of the processing chamber. The method further includes causing, based on the one or more outputs, performance of one or more corrective actions associated with the processing chamber.

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: A beamforming apparatus is constructed from a pliable medium and a conductor pattern disposed on the pliable medium to form a foldable Rotman lens.

Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

Abstract: A beamforming apparatus is constructed from a pliable medium and a conductor pattern disposed on the pliable medium to form a foldable Rotman lens.

Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Embodiments of a gas delivery apparatus for use in a radio frequency (RF) processing apparatus are provided herein. In some embodiments, a gas delivery apparatus for use in a radio frequency (RF) processing apparatus includes: a conductive gas line having a first end and a second end; a first flange coupled to the first end; a second flange coupled to the second end, wherein the conductive gas line extends through and between the first and second flanges; and a block of ferrite material surrounding the conductive gas line between the first and second flanges.

Abstract: Structures and methods for a multi-bit phase change memory are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: An intravascular ultrasound imaging system comprises a catheter having an elongated body having a distal end and an imaging core arranged to be inserted into the elongated body. The imaging core is arranged to transmit ultrasonic energy pulses and to receive reflected ultrasonic energy pulses. The system further includes an imaging engine coupled to the imaging core and arranged to provide the imaging core with energy pulses to cause the imaging core to transmit the ultrasonic energy pulses. The energy pulses are arranged in repeated sequences and the energy pulses of each sequence have varying characteristics. The reflected pulses may be processed to provide a composite image of images resulting from each different characteristic.

Abstract: Structures and methods for a multi-bit phase change memory, are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Abstract: Access to documents by parties can be controlled as follows. First, access can be controlled in accordance with access counters associated with the parties, where the documents have one or more versions. Second, access can be controlled in accordance with access levels associated with the parties. The access level of each party is one of a first access level, a second access level, a third access level, or a fourth access level. The first, second, third, and fourth access levels are ordered from the first access level to the fourth access level such that the first access level provides a greatest degree of access to the documents and the fourth access level provides a least degree of access to the documents. Third, access can be controlled in accordance with placement of organizations within a hierarchy of organizations, where the parties are organized over the organizations.

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Abstract: Provided are gas distribution apparatus with a delivery channel having an inlet end, an outlet end and a plurality of apertures spaced along the length. The inlet end is connectable to an inlet gas source and the outlet end is connectable with a vacuum source. Also provided are gas distribution apparatus with spiral delivery channels, intertwined spiral delivery channels, splitting delivery channels, merging delivery channels and shaped delivery channels in which an inlet end and outlet end are configured for rapid exchange of gas within the delivery channels.