Patents by Inventor An-Ming Chiang

An-Ming Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Publication number: 20240178090
    Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin
  • Publication number: 20240175989
    Abstract: The present disclosure is directed to imaging LiDARs with separate transmit (Tx) and receive (Rx) optical antennas fed by different optical waveguides. This pair of optical antennas can be activated at the same time through a dual-channel optical switch network, with the Tx antenna connected to a laser source and the Rx antenna connected to a receiver. The Tx and Rx antennas can be positioned adjacent to each other, so they point to approximately the same far-field angle. No optical alignment between the Tx and Rx is necessary. This LiDAR configuration, referred to herein as pseudo-monostatic LiDAR, eliminates spurious reflections and increases the dynamic range of the LiDAR.
    Type: Application
    Filed: August 9, 2023
    Publication date: May 30, 2024
    Inventors: Tae Joon SEOK, Ming Chiang A. WU
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 11994720
    Abstract: A large-scale single-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 28, 2024
    Assignee: The Regents of the University of California
    Inventors: Tae Joon Seok, Ming Chiang A Wu
  • Publication number: 20240170414
    Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Chiang, Hsien-Ming Tu, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20240166566
    Abstract: Various embodiments include a system or platform that uses electrochemistry to upcycle waste products and low-value minerals into valuable, carbon dioxide (CO2)-neutral materials. Various embodiments may include systems and/or methods for processing material inputs using an electrochemical reactor. Various embodiments may include systems, methods, and/or devices for capturing and sequestering carbon dioxide (CO2) while producing valuable co-products.
    Type: Application
    Filed: April 5, 2022
    Publication date: May 23, 2024
    Applicant: Sublime Systems, Inc.
    Inventors: Jesse D. BENCK, Yet-Ming CHIANG, Leah D. ELLIS, Kyle DOMINGUEZ, Mariya LAYUROVA
  • Patent number: 11984486
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 11984351
    Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Shyue Lai, Gao-Ming Wu, Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20240150235
    Abstract: Reaction schemes involving acids and bases; reactors comprising spatially varying chemical composition gradients (e.g., spatially varying pH gradients), and associated systems and methods, are generally described.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 9, 2024
    Applicant: Massachusetts Institute of Technology
    Inventors: Yet-Ming Chiang, Leah Ellis, Andres Badel
  • Publication number: 20240150803
    Abstract: A non-human organism for upgrading intermediate oxidation products formed by catalytic degradation of alkanes or polystyrenes is provided. The non-human organism is genetically modified to convert the intermediate oxidation products to secondary metabolites, and in particular to include a positive feedback loop construction in the promotor system. A method includes steps of catalytically degrading alkanes or polystyrene in an oxidizing environment to form intermediate products with one or more catalysts and contacting the intermediate products with the non-human organism such that intermediate oxidation products are converted to secondary metabolites.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 9, 2024
    Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, UNIVERSITY OF KANSAS
    Inventors: Berl OAKLEY, Travis J. WILLIAMS, Yi-Ming CHIANG, Clay C. WANG, Yuhao CHEN, Swati BIJLANI, C. Elizabeth OAKLEY, Christian Anthony RABOT
  • Publication number: 20240145827
    Abstract: Systems and methods of the various embodiments may provide a battery including a rolling diaphragm configured to move to accommodate an internal volume change of one or more components of the battery. Systems and methods of the various embodiments may provide a battery housing including a rolling diaphragm seal disposed between an interior volume of the battery and an electrode assembly within the battery. Various embodiments may provide an air electrode assembly including an air electrode supported on a buoyant platform such that the air electrode is above a surface of a volume of electrolyte when the buoyant platform is floating in the electrolyte.
    Type: Application
    Filed: June 8, 2023
    Publication date: May 2, 2024
    Inventors: Mitchell Terrance WESTWOOD, Alexander H. SLOCUM, William Henry WOODFORD, Yet-Ming CHIANG, Ian Salmon MCKAY, Mateo Cristian JARAMILLO, Eric WEBER, Jarrod David MILSHTEIN, Liang SU, Rupak CHAKRABORTY, Rachel Elizabeth MUMMA, Marc-Antoni GOULET, Brian BEGGAN, Marco FERRARA, Theodore Alan WILEY
  • Publication number: 20240145751
    Abstract: According to one aspect, an electrochemical cell may include a positive electrode, a negative electrode, and an electrolyte separating the positive electrode and the negative electrode from one another. The positive electrode, the negative electrode, and the electrolyte may collectively store and discharge energy by an electrode reaction of chlorine dioxide (ClO2).
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: Liang SU, Yet-Ming CHIANG, Merrill K. CHIANG
  • Patent number: 11969795
    Abstract: Support structures are used in certain additive fabrication processes to permit fabrication of a greater range of object geometries. For additive fabrication processes with materials that are subsequently sintered into a final part, an interface layer is formed between the object and support in order to inhibit bonding between adjacent surfaces of the support structure and the object during sintering.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 30, 2024
    Assignee: Desktop Metal, Inc.
    Inventors: Jonah Samuel Myerberg, Ricardo Fulop, Michael Andrew Gibson, Matthew David Verminski, Richard Remo Fontana, Christopher Allan Schuh, Yet-Ming Chiang, Anastasios John Hart
  • Patent number: 11973254
    Abstract: An electrochemical cell and battery system including cells, each cell including a catholyte, an anolyte, and a separator disposed between the catholyte and anolyte and that is permeable to the at least one ionic species (for example, a metal cation or the hydroxide ion). The catholyte solution includes a ferricyanide, permanganate, manganate, sulfur, and/or polysulfide compound, and the anolyte includes a sulfide and/or polysulfide compound. These electrochemical couples may be embodied in various physical architectures, including static (non-flowing) architectures or in flow battery (flowing) architectures.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 30, 2024
    Assignee: FORM ENERGY, INC.
    Inventors: Liang Su, Wei Xie, Yet-Ming Chiang, William Henry Woodford, Lucas Cohen, Jessa Silver, Katelyn Ripley, Eric Weber, Marco Ferrara, Mateo Cristian Jaramillo, Theodore Alan Wiley
  • Publication number: 20240132400
    Abstract: Reaction schemes involving acids and bases; reactors comprising spatially varying chemical composition gradients (e.g., spatially varying pH gradients), and associated systems and methods, are generally described.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Applicant: Massachusetts Institute of Technology
    Inventors: Yet-Ming Chiang, Leah Ellis, Andres Badel
  • Publication number: 20240133054
    Abstract: Chemical reaction devices involving acid and/or base, and related systems and methods, are generally described.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Applicant: Massachusetts Institute of Technology
    Inventors: Yet-Ming Chiang, Leah Ellis, Andres Badel, Isaac W. Metcalt
  • Patent number: D1024959
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 30, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh
  • Patent number: D1026816
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 14, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh
  • Patent number: D1026817
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 14, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh