Patents by Inventor An-Yu CHANG
An-Yu CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
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Publication number: 20240172433Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chih-Yu CHANG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
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Publication number: 20240172131Abstract: Methods and devices configured to determine, for a slot including a plurality of symbols allocated for downlink data, a downlink data block allocation scheme with a number of blocks of downlink data that remain constant or monotonically decrease starting at a designated symbol of the plurality of symbols allocated for downlink data; generate a voltage profile corresponding to the downlink data block allocation scheme, where the voltage profile includes a plurality of bias voltages; and apply a bias voltage selected from the plurality of bias voltages to a power amplifier in a transmission chain of the base station.Type: ApplicationFiled: June 25, 2021Publication date: May 23, 2024Inventors: Wayne BALLANTYNE, Chuanzhao YU, Ali AZAM, Gregory CHANCE, Lichung Tony CHANG
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Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20240170896Abstract: A composite mounting type electrical connector includes an insulating shell, a plurality of terminals and a plurality of shielding members. The plurality of terminals are arranged in two rows parallel to each other, and a plurality of shielding members are arranged between the two rows of terminals and separated from each other by a predetermined distance to form insulation. The two rows of terminals are soldered to a circuit board by surface mounting technology and dual in line package process respectively. The ground terminals in the two columns of terminals are commonly connected to a shield spacer to form a common ground structure. The power terminals in the two columns of terminals are commonly connected to another shielding member to form a parallel connecting structure. The shielding members produce a shielding effect between two rows of terminals, which can prevent crosstalk therebetween.Type: ApplicationFiled: May 27, 2023Publication date: May 23, 2024Inventors: MING LUO, YUNG- CHANG LIN, YU-HUNG LIN, HUNG-TIEN CHANG, HSUAN HO CHUNG
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Publication number: 20240170913Abstract: A surface light emitting element with high heat dissipation and uniform light emission includes a metal reflective layer, a first metal conductive layer, an omnidirectional reflecting current isolation layer, a first-type semiconductor current spreading layer, a light emitting diode layer, a second-type semiconductor current spreading layer and a second metal conductive layer. The metal reflective layer includes at least one surrounding wall structure. The omnidirectional reflecting current isolation layer is arranged on the metal reflective layer and entirely covers the two sides of the at least one surrounding wall structure to form at least one cylindrical channel. The light emitting diode layer is located in the at least one cylindrical channel.Type: ApplicationFiled: November 18, 2022Publication date: May 23, 2024Inventors: Chih-Sung CHANG, Wei-Yu YEN, Wayne JAN, Tau-Jin WU
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Publication number: 20240170506Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
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Publication number: 20240170381Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20240168374Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, exposing the photoresist layer to an EUV radiation, and developing the exposed photoresist layer. The photoresist layer has a composition including a metal complex including a metallic core and at least one ligand bonded to the metallic core. The at least one ligand includes an alkenyl group, an alkynyl group, or a combination thereof.Type: ApplicationFiled: January 10, 2023Publication date: May 23, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: An-Ren ZI, Ching-Yu CHANG
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Publication number: 20240164649Abstract: A physiological signal measuring method includes a training's thermal image providing step, a training step, a classification model generating step, a measurement's thermal image providing step, a mask-wearing classifying step, a block identifying step and a measurement result generating step. The measurement's thermal image providing step includes providing a measurement's thermal image, which is an infrared thermal video for measuring. The measurement result generating step includes generating a measurement result of at least one physiological parameter of the subject according to a plurality of signals of the forehead block, and the mask block or the nasal cavity block.Type: ApplicationFiled: May 28, 2023Publication date: May 23, 2024Inventors: Chuan-Yu CHANG, Yen-Qun GAO
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Patent number: 11989077Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.Type: GrantFiled: July 16, 2022Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Hung-Wei Wu, Chih-Yu Chang
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Patent number: 11990258Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler, and a titanium-containing dielectric filler. The polymer matrix has a fluoropolymer. The titanium-containing dielectric filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing dielectric filler accounts to for 5-15% by volume of the PTC material layer.Type: GrantFiled: September 28, 2022Date of Patent: May 21, 2024Assignee: POLYTRONICS TECHNOLOGY CORP.Inventors: Hsiu-Che Yen, Yung-Hsien Chang, Cheng-Yu Tung, Chen-Nan Liu, Chia-Yuan Lee, Yu-Chieh Fu, Yao-Te Chang, Fu-Hua Chu
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Patent number: 11990494Abstract: A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.Type: GrantFiled: July 22, 2021Date of Patent: May 21, 2024Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu
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Patent number: 11990443Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.Type: GrantFiled: April 9, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
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Patent number: 11988831Abstract: A method of displaying a rear-view image and a mobile device using the method are provided. The method includes: receiving the rear-view image; displaying a virtual dashboard through a display; and displaying the rear-view image on a default area of the virtual dashboard in response to receiving a signal associated with a direction indicator light, wherein the default area corresponds to the direction indicator light.Type: GrantFiled: February 14, 2023Date of Patent: May 21, 2024Assignee: Kinpo Electronics, Inc.Inventors: Yu Chi Chen, Hsien Chung Chen, Sheng-Chang Wu
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Patent number: 11991479Abstract: The disclosure provides a time-lapse photographic device. The time-lapse photographic device includes a camera module, a drive module, an environment detection module, and a control unit. The drive module is connected to the camera module to drive the camera module to rotate. The environment detection module is configured to detect an external environment of the time-lapse photographic device to generate an environment detection signal. The control unit is electrically connected to the camera module, the drive module, and the environment detection module. The control unit generates, according to a shooting stop parameter, a plurality of intermittent drive signals to control the drive module, and controls the camera module to shoot at intervals of the drive signals. The control unit adjusts operation of at least one of the camera module and the drive module according to the environment detection signal.Type: GrantFiled: February 15, 2022Date of Patent: May 21, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Hsin-Yi Pu, Kai-Yu Hsu, Lai-Peng Wong, Chieh Li, Ting-Han Chang, Ching-Xsuan Chen
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Patent number: 11991888Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.Type: GrantFiled: June 29, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 11991485Abstract: A projection apparatus including a projection device, a reflecting component, and an image capturing device is provided. The projection device is adapted to project an image light beam to form a projection image. The reflecting component is disposed on the projection device and has a reflecting surface. The image capturing device is disposed on the projection device and has an image capturing end. The image capturing end faces the reflecting surface. The reflecting surface is adapted to reflect the projection image to the image capturing end.Type: GrantFiled: July 12, 2022Date of Patent: May 21, 2024Assignee: Coretronic CorporationInventors: Jen-Yu Shie, Kuang-Hsiang Chang, Hung-Pin Chen, Heng Li
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Patent number: 11991932Abstract: A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.Type: GrantFiled: May 18, 2021Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Yu Chang, Min-Yung Ko
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Publication number: 20240156413Abstract: An apparatus and a method for detecting heartbeat include a sensor configured to detect displacements of an object without contacting the object wherein the object displaces corresponding the a human's heartbeat, a data processing unit configured to extract a feature dataset from the detected displacement data, and a neural network configured to inference inter beat intervals from the extracted feature dataset using a pre-trained model.Type: ApplicationFiled: November 8, 2022Publication date: May 16, 2024Applicant: WISTRON CORPORATIONInventors: Yin-Yu CHEN, Kai Jen CHENG, Yao-Tsung CHANG