Abstract: An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).

Abstract: A radio communication device includes a device substrate. A transmitter circuit is coupled to the device substrate to transmit a radio frequency signal to an antenna. The radio communication device also includes a receiver circuit coupled to the device substrate, where the receiver circuit includes an oscillator circuit to generate a baseband signal from a received radio frequency signal. The radio communication device further includes a feedback circuit coupled to the antenna and to the receiver circuit, where the feedback circuit couples a portion of the transmitted radio frequency signal to the oscillator circuit using a transmission line.

Abstract: An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).

Abstract: Aspects of the disclosure pertain to a system and method for providing controllable steady state current waveshaping in a preamplifier of a data storage system (e.g., hard disk drive). The preamplifier provides an output including a write current waveform having a steady state current level that is controllable via the write block circuitry of the preamplifier. This enhances the ability of the waveform to promote improved on-track and off-track write performance.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises degauss circuitry coupled to or otherwise associated with one or more write drivers. The degauss circuitry is configured to generate an asymmetric degauss signal to be applied to the write head. The asymmetric degauss signal has a waveform with upper and lower decay envelopes that are asymmetric about a specified degauss current level, such as a substantially zero current level.

Abstract: Aspects of the disclosure pertain to a system and method for providing controllable steady state current waveshaping in a preamplifier of a data storage system (e.g., hard disk drive). The preamplifier provides an output including a write current waveform having a steady state current level that is controllable via the write block circuitry of the preamplifier. This enhances the ability of the waveform to promote improved on-track and off-track write performance.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising a write pulse, and reflection compensation circuitry coupled to or otherwise associated with the write driver and configured to provide one or more reflection compensation pulses in the write pulse.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a chirped degauss signal to be applied to the write head by the write driver. The degauss circuitry comprises a ramp generator configured to generate a ramp signal for controlling a frequency of at least a portion of a waveform of the chirped degauss signal. The ramp signal generated by the ramp generator may comprise a current ramp that is applied to a control input of a current controlled oscillator of the degauss circuitry.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a degauss signal to be applied to the write head by the write driver. The degauss signal has a waveform comprising a plurality of decay segments including at least one alternating current decay segment and at least one direct current decay segment. An initial decay segment of the plurality of decay segments may comprise an alternating current decay segment or a direct current decay segment, and may be immediately followed by a decay segment of the opposite type.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a degauss signal to be applied to the write head by the write driver. The degauss signal has a waveform comprising a plurality of decay segments including at least one alternating current decay segment and at least one direct current decay segment. An initial decay segment of the plurality of decay segments may comprise an alternating current decay segment or a direct current decay segment, and may be immediately followed by a decay segment of the opposite type.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a chirped degauss signal to be applied to the write head by the write driver. The degauss circuitry comprises a ramp generator configured to generate a ramp signal for controlling a frequency of at least a portion of a waveform of the chirped degauss signal. The ramp signal generated by the ramp generator may comprise a current ramp that is applied to a control input of a current controlled oscillator of the degauss circuitry.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Abstract: Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity.

Abstract: Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity.

Abstract: Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.