Patents by Inventor Anand Arunachalam

Anand Arunachalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for automatic relative placement generation for clock trees
    Patent number: 9792396
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 17, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Anand Arunachalam
  • METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
    Publication number: 20160335376
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Applicant: SYNOPSYS, INC.
    Inventor: ANAND ARUNACHALAM
  • Method and apparatus for automatic relative placement generation for clock trees
    Patent number: 9430601
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: SYNOPSYS, INC.
    Inventor: Anand Arunachalam
  • Placement of single-bit and multi-bit flip-flops
    Patent number: 9361417
    Abstract: Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 7, 2016
    Assignee: Synopsys, Inc.
    Inventors: Anand Arunachalam, Suman Chatterjee, Jing C. Lin
  • PLACEMENT OF SINGLE-BIT AND MULTI-BIT FLIP-FLOPS
    Publication number: 20150227646
    Abstract: Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 13, 2015
    Applicant: SYNOPSYS, INC.
    Inventors: Anand Arunachalam, Suman Chatterjee, Jing C. Lin
  • METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
    Publication number: 20150213159
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 30, 2015
    Applicant: SYNOPSYS, INC.
    Inventor: Anand Arunachalam
  • Method and apparatus for automatic relative placement generation for clock trees
    Patent number: 8984467
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 17, 2015
    Assignee: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Method and apparatus for automatic relative placement rule generation
    Patent number: 8751986
    Abstract: Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Synopsys, Inc.
    Inventors: Anand Arunachalam, Mustafa Kamal, Xinwei Zheng, Mohammad Khan, Xiaoyan Yang, Dongxiang Wu
  • Relative positioning of circuit elements in circuit design
    Patent number: 8434035
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: April 30, 2013
    Assignee: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
    Publication number: 20130047127
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Applicant: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Relative Positioning of Circuit Elements in Circuit Design
    Publication number: 20120284682
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
    Type: Application
    Filed: July 5, 2012
    Publication date: November 8, 2012
    Applicant: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Relative positioning of circuit elements in circuit design
    Patent number: 8239792
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: August 7, 2012
    Assignee: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Method and Apparatus for Automatic Relative Placement Rule Generation
    Publication number: 20120036488
    Abstract: Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 9, 2012
    Applicant: Synopsys, Inc.
    Inventors: Anand Arunachalam, Mustafa Kamal, Xinwei Zheng, Mohammad Khan, Xiaoyan Yang, Dongxiang Wu
  • Method and apparatus for automatic orientation optimization
    Patent number: 7937682
    Abstract: Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: May 3, 2011
    Assignee: Synopsys, Inc.
    Inventors: Anand Arunachalam, Mahesh Anantharaman Iyer
  • Relative Positioning of Circuit Elements in Circuit Design
    Publication number: 20090313594
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
    Type: Application
    Filed: July 20, 2009
    Publication date: December 17, 2009
    Applicant: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Relative positioning of circuit elements in circuit design
    Patent number: 7581197
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuits design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: August 25, 2009
    Assignee: Synopsys, Inc.
    Inventor: Anand Arunachalam
  • Method and Apparatus for Automatic Orientation Optimization
    Publication number: 20090199142
    Abstract: Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.
    Type: Application
    Filed: July 31, 2008
    Publication date: August 6, 2009
    Applicant: Synopsys, Inc.
    Inventors: Anand Arunachalam, Mahesh Anantharaman Iyer
  • Relative positioning of circuit elements in circuit design
    Publication number: 20060271894
    Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology.
    Type: Application
    Filed: May 26, 2005
    Publication date: November 30, 2006
    Applicant: Synopsys, Inc.
    Inventor: Anand Arunachalam