Abstract: A system and method are provided for enforcing user policies on database. In one aspect a user policy and/or enterprise policy is predefined and mapped to the column of the database. Further, the query is run through a query parsing module, the result is sent to a query analyzing module to analyze the sensitivity of each query. A query rewriting module rewrites the query and the rewritten query is sent to the database. A sensitive tree is generated using database metadata, which is used during query analysis and query re-writing. In cases the original query does not contain any set operators the rewritten query is executed on the database and results are displayed as per the user policy. The cases where the original query comprises set operators a function called merger is implemented in the database or at the proxy server and data is displayed as per the user policy.

Abstract: A system and a method for managing privacy of data are provided. The method includes causing generation of a trigger notification notifying an access to one or more fields of a user-profile in a first application. The trigger notification generated is by a second application integrated with the first application. The first application includes a plurality of fields comprising sensitive data associated with the user-profile. The method further includes enforcing one or more access preferences corresponding to the one or more fields by the second application on the generation of the trigger notification. The one or more access preferences are based at least on one of a plurality of preconfigured rules and contextual information associated with the trigger notification. Enforcing the one or more access preferences facilitates in managing data privacy.

Abstract: A system and method are provided for enforcing user policies on database. In one aspect a user policy and/or enterprise policy is predefined and mapped to the column of the database. Further, the query is run through a query parsing module, the result is sent to a query analyzing module to analyze the sensitivity of each query. A query rewriting module rewrites the query and the rewritten query is sent to the database. A sensitive tree is generated using database metadata, which is used during query analysis and query re-writing. In cases the original query does not contain any set operators the rewritten query is executed on the database and results are displayed as per the user policy. The cases where the original query comprises set operators a function called merger is implemented in the database or at the proxy server and data is displayed as per the user policy.

Abstract: A system and a method for managing privacy of data are provided. The method includes causing generation of a trigger notification notifying an access to one or more fields of a user-profile in a first application. The trigger notification generated is by a second application integrated with the first application. The first application includes a plurality of fields comprising sensitive data associated with the user-profile. The method further includes enforcing one or more access preferences corresponding to the one or more fields by the second application on the generation of the trigger notification. The one or more access preferences are based at least on one of a plurality of preconfigured rules and contextual information associated with the trigger notification. Enforcing the one or more access preferences facilitates in managing data privacy.

Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer.

Abstract: A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed.

Abstract: A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.

Abstract: A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed.

Abstract: A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled to the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state of the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer.

Abstract: A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.

Abstract: A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.

Abstract: The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.