Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.

Abstract: A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract: An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.

Abstract: A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

Abstract: A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract: A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.