Patents by Inventor Anand Kannan
Anand Kannan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989772Abstract: A system for extracting a product information of assets from the low resolution media contents taken in an environment 104 and updating a global product-master database 110 with the extracted product information is provided. An image capturing device 102 captures the media contents of assets. The product information extraction system 106 that (i) receives the media contents from the device 102, (ii) identifies the low resolution media contents based on size and dimensions of media contents, (iii) parses the low resolution media contents, using a system of cascading deep neural networks, to generate the product information at Stock Keeping Unit (SKU) level, (iv) transfers the product information obtained from the deep neural network system to the point of sale device 108 to update a local point-of-sale product-master, and (v) transmits the product information to the a global product-master server to update the global product-master database 110.Type: GrantFiled: July 5, 2020Date of Patent: May 21, 2024Assignee: INFILECT TECHNOLOGIES PRIVATE LIMITEDInventors: Vijay Gabale, Anand Prabhu Subramanian, Vijaykumar Kannan
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Patent number: 11676115Abstract: An authorization system includes a database, and at least one computer server in communication with the database. The database includes a plurality of database records, each including an account number and an associated card number. Each card number has fewer digits than the associated account number. The server is configured to receive, from a communications terminal, a request message that initiates a transaction with the server. The server is configured to request an authentication credential from the terminal, and in the database locate the card number that matches the received authentication credential and locate the account number that is associated with the located card number. The server is configured to request authorization of a test transaction using the account number, receive an authorization response confirming authorization of the test transaction, and authorize the initiated transaction in response to the authorization response. The test transaction is different from the initiated transaction.Type: GrantFiled: June 29, 2020Date of Patent: June 13, 2023Assignee: The Toronto-Dominion BankInventors: Hisham Salama, Lauren Van Heerden, Ian Sundberg, Anand Kannan, Orin Del Vecchio
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Patent number: 11509217Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.Type: GrantFiled: November 17, 2020Date of Patent: November 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anandha Ruban Tiruchengode Tirumurugga Bupathi, Anand Kannan, Dileep Kumar Ramesh Bhat
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Piecewise Correction of Errors Over Temperature without Using On-Chip Temperature Sensor/Comparators
Publication number: 20220350360Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Praful Kumar Parakh, Anand Kannan, Sunil Rafeeque -
Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators
Patent number: 11409317Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.Type: GrantFiled: April 25, 2018Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Praful Kumar Parakh, Anand Kannan, Sunil Rafeeque -
Patent number: 11152904Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.Type: GrantFiled: February 13, 2020Date of Patent: October 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Subramanian, Tanmay Halder, Anand Kannan
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Publication number: 20210075320Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.Type: ApplicationFiled: November 17, 2020Publication date: March 11, 2021Inventors: Anandha Ruban TIRUCHENGODE TIRUMURUGGA BUPATHI, Anand KANNAN, Dileep Kumar RAMESH BHAT
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Publication number: 20210044267Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.Type: ApplicationFiled: February 13, 2020Publication date: February 11, 2021Inventors: Anand SUBRAMANIAN, Tanmay HALDER, Anand KANNAN
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Patent number: 10911004Abstract: A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.Type: GrantFiled: June 24, 2019Date of Patent: February 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Subramanian, Anand Kannan
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Patent number: 10892770Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.Type: GrantFiled: October 30, 2019Date of Patent: January 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tanmay Halder, Anand Kannan
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Patent number: 10873259Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.Type: GrantFiled: October 29, 2019Date of Patent: December 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anandha Ruban Tiruchengode Tirumurugga Bupathi, Anand Kannan, Dileep Kumar Ramesh Bhat
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Publication number: 20200327513Abstract: An authorization system includes a database, and at least one computer server in communication with the database. The database includes a plurality of database records, each including an account number and an associated card number. Each card number has fewer digits than the associated account number. The server is configured to receive, from a communications terminal, a request message that initiates a transaction with the server. The server is configured to request an authentication credential from the terminal, and in the database locate the card number that matches the received authentication credential and locate the account number that is associated with the located card number. The server is configured to request authorization of a test transaction using the account number, receive an authorization response confirming authorization of the test transaction, and authorize the initiated transaction in response to the authorization response. The test transaction is different from the initiated transaction.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: HISHAM SALAMA, Lauren VAN HEERDEN, Ian SUNDBERG, Anand KANNAN, Orin DEL VECCHIO
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Publication number: 20200304139Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.Type: ApplicationFiled: October 23, 2019Publication date: September 24, 2020Inventors: Uttam Kumar AGARWAL, Anand KANNAN, Ramamurthy VISHWESHWARA, Anand SUBRAMANIAN, Pedro Ramon GELABERT, Diljith Mathal THODI, Abhijit Anant PATKI
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Patent number: 10763889Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.Type: GrantFiled: October 23, 2019Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Uttam Kumar Agarwal, Anand Kannan, Ramamurthy Vishweshwara, Anand Subramanian, Pedro Ramon Gelabert, Diljith Mathal Thodi, Abhijit Anant Patki
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Patent number: 10747249Abstract: A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.Type: GrantFiled: June 21, 2019Date of Patent: August 18, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Subramanian, Anand Kannan
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Publication number: 20200259492Abstract: A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Priyank ANAND, Anand KANNAN, Venkatesh GUDURI
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Patent number: 10726400Abstract: A method of authorizing a transaction involves a computer server authenticating a payment cardholder from a cardholder credential, and receiving a request from a communications terminal to initiate an online transaction with the server. The server communicates with a database of clusters, each uniquely associated with a respective cardholder and identifying an authentication card and a partial payment card number. The server requests an authentication credential from the terminal in response to determining that the requested transaction possesses a high risk of fraud. The server receives the requested authentication credential, and uses the cardholder and authentication credentials to locate the authentication card uniquely associated with the cardholder and the authentication credential in the database. The authentication credential has fewer digits than the account number of the located authentication card.Type: GrantFiled: June 10, 2014Date of Patent: July 28, 2020Assignee: The Toronto-Dominion BankInventors: Hisham Salama, Lauren Van Heerden, Ian Sundberg, Anand Kannan, Orin Del Vecchio
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Patent number: 10680608Abstract: A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.Type: GrantFiled: August 8, 2016Date of Patent: June 9, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Priyank Anand, Anand Kannan, Venkatesh Guduri
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Publication number: 20200136507Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Inventors: Anandha Ruban TIRUCHENGODE TIRUMURUGGA BUPATHI, Anand KANNAN, Dileep Kumar RAMESH BHAT
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Publication number: 20200136638Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.Type: ApplicationFiled: October 30, 2019Publication date: April 30, 2020Inventors: Tanmay HALDER, Anand KANNAN