Abstract: Systems and methods for reducing hot spots and recovering Vt/area to improve chip performance in an integrated circuit design. According to the method, physical grid areas for an IC chip are defined and a switching window for library elements of an integrated circuit design in a region of the chip is determined. Points of peak current for library elements within the switching window are determined. A grid area is selected and library elements having additional usable timing margin are identified. The library elements are prioritized, based on location in the grid area according to peak current and usable timing margin. Based on order of priority, the timing of signal paths in the grid area may be adjusted in order to misalign points of peak current and maintain current density in the region below a threshold and/or a library element within the grid area may be changed to recover area within the grid area.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: In one embodiment, at least one design library element having a design marker shape is applied to a yield checking tool having library element types, each having a yield checking deck threshold and a marker shape. The design marker shape is compared to each of the marker shapes. A determination is made as to whether the design library element satisfies the yield checking deck threshold associated with the library element type having a matching marker shape. In another embodiment, a product design formed from a design library elements each having a design marker shape is applied to the yield checking tool in a similar manner. In instances where the design library elements do not satisfy the yield checking deck threshold, then the design library element is updated by modifying the design library elements, placement of the design library elements in the product design, and/or wiring connecting the design library elements.