Patents by Inventor Anand Ramalingam

Anand Ramalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220012094
    Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 13, 2022
    Applicant: Intel Corporation
    Inventors: Shirish Bahirat, Anand Ramalingam, Anjaneya Chagam Reddy
  • Publication number: 20220004335
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Applicant: Intel Corporation
    Inventors: Mohammad Nasim Imtiaz Khan, Yogesh B. Wakchaure, Eric Hoffman, Neal Mielke, Shirish Bahirat, Cole Uhlman, Ye Zhang, Anand Ramalingam
  • Publication number: 20210392083
    Abstract: Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 16, 2021
    Inventors: Shirish Bahirat, Anand Ramalingam, Solomon Sagar Albert Jayaraj, Fnu Sachin, Xin Guo
  • Patent number: 11137916
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Publication number: 20210294698
    Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Ali Khakifirooz, George Kalwitz, Anand Ramalingam, Ravi Motwani, Renjie Chen
  • Patent number: 11068175
    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Marcin Pioch, Michael Mesnier, Anand Ramalingam, Benjamin Boyer, Kapil Karkra, Piotr Wysocki
  • Patent number: 10296250
    Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Benjamin L. Walker, August A. Camber, Jonathan Bryan Stern, Sanjeev Trika, Richard P. Mangold, Jawad Basit Khan, Anand Ramalingam
  • Publication number: 20190146698
    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Marcin Pioch, Michael Mesnier, Anand Ramalingam, Benjamin Boyer, Kapil Karkra, Piotr Wysocki
  • Publication number: 20190042114
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Publication number: 20170357462
    Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Benjamin L. Walker, August A. Camber, Jonathan Bryan Stern, Sanjeev Trika, Richard P. Mangold, Jawad Basit Khan, Anand Ramalingam
  • Patent number: 8234937
    Abstract: A torque sensor includes an adjustable platform vertically adjustable to place a sensing module near a rotating target to obtain measurements there from with a sensing element. The apparatus can be configured to include a bottom channel mounted to a base and a PCB tray mounted to a top channel, the PCB tray and top channel vertically adjustable from the base by a rotating shaft. The top and bottom channels are coupled to side bars and side channels in pairs movably connected by joint pins with a rotatable shaft movably connecting said joint pins. The sensing module is movable with respect to the base via rotation of said rotatable shaft causing movement of said pair of side bars and side channels, placing said sensing element nearest a target to obtain rotational movement data.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: August 7, 2012
    Assignee: Honeywell International Inc.
    Inventor: Prem Anand Ramalingam
  • Publication number: 20110029257
    Abstract: A torque sensor includes an adjustable platform vertically adjustable to place a sensing module near a rotating target to obtain measurements there from with a sensing element. The apparatus can be configured to include a bottom channel mounted to a base and a PCB tray mounted to a top channel, the PCB tray and top channel vertically adjustable from the base by a rotating shaft. The top and bottom channels are coupled to side bars and side channels in pairs movably connected by joint pins with a rotatable shaft movably connecting said joint pins. The sensing module is movable with respect to the base via rotation of said rotatable shaft causing movement of said pair of side bars and side channels, placing said sensing element nearest a target to obtain rotational movement data.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 3, 2011
    Inventor: Prem Anand Ramalingam
  • Publication number: 20100257944
    Abstract: A torque sensor adjustable platform apparatus is configured to include a base with a centering block between two linear grooves. Two sliders slide along the linear grooves under the control of a lead screw. Turning the lead screw causes the sliders to either approach each other or to separate. A PCB tray rides on top of the sliders. The tops of the sliders have retaining grooves keyed to accept retaining rails on the bottom of the PCB tray. The retaining grooves and retaining rails are angled so that the PCB tray moves further from the base as the sliders approach one another. A receiving module fixed into the PCB tray receives a signal from a shaft mounted torque sensor. The lead screw can be manipulated to optimizing the received signal while keeping the receiving module clear of the shaft.
    Type: Application
    Filed: April 9, 2009
    Publication date: October 14, 2010
    Inventors: Prem Anand Ramalingam, Max C. Jarrell