Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

Abstract: According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.