Abstract: A semiconductor memory device having a redundancy scheme is disclosed. A memory cell array includes a number of standard word lines sets and at least one redundant word line set. Each standard word line within a standard word line set is selected by lower address signals, and couples memory cells to a different combination of bit line than the other standard word lines within the standard word line set. In a standard mode of operation, transfer gates coupled to each bit line are enabled according to the lower address signals. Each redundant word line within a redundant word line set is selected by a defective address, and couples memory cells to a different combination of bit lines than the other redundant word lines within the redundant word line set. In a redundant mode of operation, the transfer gates are enabled according to an activated redundant word line to ensure that the proper combination of bit lines is coupled to sense amplifier circuits.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).