Patents by Inventor Anand Venkitasubramani
Anand Venkitasubramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056448Abstract: Systems or methods of the present disclosure may provide a system that includes a secure processor subsystem that includes a processor and a first programmable lookup table. The first programmable lookup table is to receive global identifiers for initiators of operations using a resource and to translate the global identifiers to respective local identifiers for use in the secure processor subsystem. The initiators are external to the secure processor subsystem. The secure processor subsystem also includes a second programmable lookup table to translate the local identifiers to respective global identifiers for egresses from the secure processor subsystem.Type: ApplicationFiled: September 29, 2023Publication date: February 15, 2024Inventors: Anand Venkitasubramani, Michael Carl Neve de Mevergnies
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Publication number: 20230309163Abstract: A communication device may include a processor configured to establish a connection with one or more peripheral devices in response to a disconnection from an external communication device, determine that the external communication device is connectable based on radio communication signals received from the external communication device, and encode a message to be transmitted to the one or more peripheral devices in response to the determination that the external communication device is connectable, wherein the message is configured to cause the one or more peripheral devices to perform a high duty cycle advertising in accordance with a Bluetooth communication protocol.Type: ApplicationFiled: January 31, 2023Publication date: September 28, 2023Inventors: Harish MITTY, Anand VENKITASUBRAMANI, Satish G. U., Abhijeet Prabhakar PALNITKAR, Balvinder Pal SINGH
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Publication number: 20230108339Abstract: Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.Type: ApplicationFiled: December 7, 2022Publication date: April 6, 2023Inventors: Krishna Kumar Nagar, Nathan Krueger, Yi Peng, Brandon Lewis Gordon, Anand Venkitasubramani
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Patent number: 11563409Abstract: Some embodiments herein describe a radio frequency communication system that can include a transmitter to output an radio frequency (RF) transmit signal, the transmitter including a digital pre-distortion system (DPD) that pre-distorts the RF transmit signal. The DPD system can include a configurable non-linear filter, such as a Laguerre filter, having multiple rows where at least one row operates with a configurable decimation ratio. The DPD system can further include decimators and a crossbar switch coupled between the decimators.Type: GrantFiled: June 22, 2021Date of Patent: January 24, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Anand Venkitasubramani, Stephen Summerfield, Bhavana Muralikrishna, Praveen Chandrasekaran
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Patent number: 11463715Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.Type: GrantFiled: March 17, 2021Date of Patent: October 4, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Anand Venkitasubramani, Bhavana Muralikrishna, Shreeja Sugathan, Niall D. O'Connell
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Publication number: 20220131506Abstract: Some embodiments herein describe a radio frequency communication system that can include a transmitter to output an radio frequency (RF) transmit signal, the transmitter including a digital pre-distortion system (DPD) that pre-distorts the RF transmit signal. The DPD system can include a configurable non-linear filter, such as a Laguerre filter, having multiple rows where at least one row operates with a configurable decimation ratio. The DPD system can further include decimators and a crossbar switch coupled between the decimators.Type: ApplicationFiled: June 22, 2021Publication date: April 28, 2022Inventors: Anand Venkitasubramani, Stephen Summerfield, Bhavana Muralikrishna, Praveen Chandrasekaran
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Publication number: 20210203966Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.Type: ApplicationFiled: March 17, 2021Publication date: July 1, 2021Applicant: Analog Devices International Unlimited CompanyInventors: Anand VENKITASUBRAMANI, Bhavana MURALIKRISHNA, Shreeja SUGATHAN, Niall D. O'Connell
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Patent number: 10972744Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.Type: GrantFiled: November 12, 2018Date of Patent: April 6, 2021Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Anand Venkitasubramani, Bhavana Muralikrishna, Shreeja Sugathan, Niall D. O'Connell
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Publication number: 20200154120Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.Type: ApplicationFiled: November 12, 2018Publication date: May 14, 2020Applicant: Analog Devices International Unlimited CompanyInventors: Anand VENKITASUBRAMANI, Bhavana MURALIKRISHNA, Shreeja SUGATHAN, Niall D. O'Connell
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Patent number: 8130886Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.Type: GrantFiled: January 9, 2008Date of Patent: March 6, 2012Assignee: Analog Devices, Inc.Inventors: Anand Venkitasubramani, Sudheesh A.S
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Publication number: 20090174471Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Anand Venkitasubramani, Sudheesh A.S