Patents by Inventor Ananda K. Banerji
Ananda K. Banerji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230112746Abstract: Various embodiments herein relate to methods, apparatus, and systems for depositing a boron-based ceramic film on a substrate. Advantageously, the boron-based ceramic films described herein can be formed at relatively low temperatures (e.g., about 600C or less), while still achieving very high quality materials that exhibit good mechanical strength (e.g., high hardness and Young's modulus), good etch selectivity, amorphous morphology, etc. The films herein also have low hydrogen content, low oxygen content, and low halide content. In many cases, the films may be formed through a reaction between a boron halide and a saturated or unsaturated hydrocarbon, in the presence of plasma.Type: ApplicationFiled: February 23, 2021Publication date: April 13, 2023Inventors: Ananda K. BANERJI, Jon HENRI, Kapu Sirish REDDY, Christopher Nicholas IADANZA
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Publication number: 20220051938Abstract: Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.Type: ApplicationFiled: September 10, 2019Publication date: February 17, 2022Inventors: Hui-Jung Wu, Bart J. van Schravendijk, Mark Naoshi Kawaguchi, Gereng Gunawan, Jay E. Uglow, Nagraj Shankar, Gowri Channa Kamarthy, Kevin M. McLaughlin, Ananda K. Banerji, Jialing Yang, John Hoang, Aaron Lynn Routzahn, Nathan Musselwhite, Meihua Shen, Thorsten Bernd Lill, Hao Chi, Nicholas Dominic Altieri
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Patent number: 11011379Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.Type: GrantFiled: August 29, 2019Date of Patent: May 18, 2021Assignee: Lam Research CorporationInventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
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Patent number: 10763107Abstract: Methods and apparatuses suitable for encapsulation layers for memory devices at temperatures less than about 300° C. are provided herein. Methods involve introducing a reactive species by pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.Type: GrantFiled: January 10, 2020Date of Patent: September 1, 2020Assignee: Lam Research CorporationInventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji
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Publication number: 20200152452Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.Type: ApplicationFiled: January 10, 2020Publication date: May 14, 2020Inventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji
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Patent number: 10559468Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.Type: GrantFiled: May 10, 2018Date of Patent: February 11, 2020Assignee: Lam Research CorporationInventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
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Publication number: 20190385850Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
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Patent number: 10157736Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.Type: GrantFiled: September 28, 2016Date of Patent: December 18, 2018Assignee: LAM RESEARCH CORPORATIONInventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji
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Publication number: 20180269061Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.Type: ApplicationFiled: May 10, 2018Publication date: September 20, 2018Inventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
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Publication number: 20170323803Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.Type: ApplicationFiled: September 28, 2016Publication date: November 9, 2017Inventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji
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Patent number: 9379210Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.Type: GrantFiled: October 14, 2015Date of Patent: June 28, 2016Assignee: Lam Research CorporationInventors: Thomas Weller Mountsier, Bart J. van Schravendijk, Ananda K. Banerji, Nagraj Shankar
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Publication number: 20160071953Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.Type: ApplicationFiled: October 14, 2015Publication date: March 10, 2016Inventors: Thomas Weller Mountsier, Bart J. van Schravendijk, Ananda K. Banerji, Nagraj Shankar
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Patent number: 9190489Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.Type: GrantFiled: September 8, 2014Date of Patent: November 17, 2015Assignee: Lam Research CorporationInventors: Thomas Weller Mountsier, Bart J. van Schravendijk, Ananda K. Banerji, Nagraj Shankar