Patents by Inventor Ananthan Ayyasamy

Ananthan Ayyasamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY ACCESS TRACING
    Publication number: 20220334963
    Abstract: Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 20, 2022
    Inventors: Ankit PATEL, Lidia WARNES, Donald L. FAW, Bassam N. COURY, Douglas CARRIGAN, Hugh WILKINSON, Ananthan AYYASAMY, Michael F. FALLON
  • Multichip package link
    Patent number: 11003610
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobel Li, Robert G. Blankenship, Robert J. Safranek
  • MULTICHIP PACKAGE LINK
    Publication number: 20200320031
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Application
    Filed: January 31, 2020
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Multichip package link
    Patent number: 10552357
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • MULTICHIP PACKAGE LINK
    Publication number: 20180300275
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Application
    Filed: November 22, 2017
    Publication date: October 18, 2018
    Applicant: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Multichip package link
    Patent number: 10073808
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • MULTICHIP PACKAGE LINK
    Publication number: 20170083475
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Application
    Filed: December 26, 2013
    Publication date: March 23, 2017
    Applicant: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Methods and apparatus for asserting flow control at input ports of a shared-memory switch
    Patent number: 7321553
    Abstract: In a method of allocating a shared resource among a plurality of competing applicants, a share of the resource allocated to one of the applicants is limited on the basis of a current proportion of the resource allocated to the applicant and a total of respective shares of the resource currently allocated to all of the applicants.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Ajith Prasad, Ananthan Ayyasamy, Jain Philip, Paritosh Joshi
  • Methods and apparatus for asserting flow control at input ports of a shared-memory switch
    Publication number: 20050018708
    Abstract: In a method of allocating a shared resource among a plurality of competing applicants, a share of the resource allocated to one of the applicants is limited on the basis of a current proportion of the resource allocated to the applicant and a total of respective shares of the resource currently allocated to all of the applicants.
    Type: Application
    Filed: July 22, 2003
    Publication date: January 27, 2005
    Inventors: Ajith Prasad, Ananthan Ayyasamy, Jain Philip, Paritosh Joshi
  • Apparatus, system and method for limiting latency
    Publication number: 20040117791
    Abstract: A method, apparatus, and system for limiting latency.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Inventors: Ajith Prasad, Jain Philip, Ananthan Ayyasamy, Prabhanjan Moleyar