Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.

Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask

Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising: inserting a first external dummy along an external edge of the guiding pattern in a vertical direction; and inserting a second external dummy at a fixed distance from a second edge of the first external dummy, wherein the second external dummy includes a two-dimensional shape such that at least two edges of the second external dummy are parallel to the second edge of the first external dummy.

Abstract: Disclosed are techniques for processing layout designs based on dynamically-generated lithographic models. Lithographic models are determined for a plurality of regions of a reticle prior to lithographic simulation. During lithographic simulation, lithographic models for a small area within a particular region are generated based on the lithographic models for the particular region, the lithographic models for one or more neighboring regions, and location information of the small area relative to the region and to the one or more neighboring regions. The lithography models comprise illuminating and imaging system models and mask electro-magnetic field models.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising: inserting a first external dummy along an external edge of the guiding pattern in a vertical direction; and inserting a second external dummy at a fixed distance from a second edge of the first external dummy, wherein the second external dummy includes a two-dimensional shape such that at least two edges of the second external dummy are parallel to the second edge of the first external dummy.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to an edge of the first external dummy is greater than a first distance.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a guiding pattern layout, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.