Abstract: A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.

Abstract: A terminator for a transmission line that consumes substantially zero power. According to a preferred embodiment, a four device latch is provided, coupled at one side of the latch to the transmission line by way of a resistance. The size of the devices on the side of the latch connected to the transmission line and the value of the resistance are selected such that the combined impedance of the resistance and the device impedance to ground is substantially the same as the characteristic impedance of the transmission line. A proper impedance termination is provided for steady state high and steady state low conditions, as well as during substantially all of a transition there between.

Abstract: A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the serially connected stages are controlled alternatively by a true and a complemented clock signal. Preferably, there are two such loops operating in parallel but which include initialization circuitry that initializes the two loops to complementary values.

Abstract: A memory cell that allows simultaneous writing into the cell and reading from the cell. The memory cell is a cross-coupled latch in which two pairs of a load transistor and a pull-down transistor are connected at respective first and second coupling points. However, the feedback path from the first coupling point to the gate electrode of the pull-down transistor of the other pair passes through a feedback transistor which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals can be impressed upon the gate electrode of the thus separated gate electrodes. Simultaneously, the signal on the first coupling point can be selectively impressed upon any combination of a plurality of read lines. If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.

Abstract: The present invention is especially directed toward a memory cell designed for use in a register stack in which multiple independent and parallel read/write and read operations may proceed simultaneously. The cell comprises multiple write transistors and multiple read transistors all coupled to a single dynamic storage means which can be written into and read from, simultaneously.

Abstract: The present invention is especially directed towards a memory array which utilizes means for comparing the address inputs of word decoders in the system such that, when a compare occurs, selected ones of the word decoders are disabled to prevent a multiple read and selected higher order read heads are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder.

Abstract: This is a feedback amplifier incorporating shunt feedback pairs which are emitter coupled for differential input transimpedance configuration whose characteristic includes a low differential input impedance and a high common load impedance that uses low input offset voltages to initiate the amplification and a latch coupled thereto to latch and amplify the amplifier input causing the effective amplifier input to be several orders of magnitude greater than the initial offset voltages. Thus, the amplifier of the invention uses the latch to not only sense the output of the amplifier but also the drive and reinforce the amplifier input through feedback.

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g.