Abstract: In some aspects, the disclosure is directed to methods and systems for interference mitigation and cancellation in full duplex amplifiers for cable modem or broadband communication systems. In many implementations, an interference canceller in the downstream path may be provided to equalize composite power on the FDX upstream subbands within a predetermined range of amplitude (e.g. X dB) from the desired downstream signal on the same subband, without affecting the downstream subbands.

Abstract: A full duplex repeater includes an upstream echo canceller and noise reduction circuitry. The noise reduction circuitry is configured to receive an upstream signal from the upstream echo canceller, separate the upstream signal into a plurality of Fast Fourier Transform (FFT) blocks, multiply the upstream signal by a 100% raised cosine window, convert the upstream signal into frequency domain using FFT, clean predetermined portions of the upstream signal in the FFT blocks based on a predetermined threshold, convert the upstream signal from frequency domain to time domain using Inverse FFT; and recombine the FFT blocks.

Abstract: A full duplex repeater includes an upstream echo canceller and noise reduction circuitry. The noise reduction circuitry is configured to receive an upstream signal from the upstream echo canceller, separate the upstream signal into a plurality of Fast Fourier Transform (FFT) blocks, multiply the upstream signal by a 100% raised cosine window, convert the upstream signal into frequency domain using FFT, clean predetermined portions of the upstream signal in the FFT blocks based on a predetermined threshold, convert the upstream signal from frequency domain to time domain using Inverse FFT; and recombine the FFT blocks.

Abstract: In some aspects, the disclosure is directed to methods and systems for improving signal to noise ratios of signals from multiple communication links. In some embodiments, a system includes a first frequency transformation circuit configured to transform a first signal in a time domain received from a first device into a corresponding second signal in a frequency domain. The system further includes a second frequency transformation circuit configured to transform a third signal in the time domain received from a second device into a corresponding fourth signal in the frequency domain. The system further includes a leg combining circuit configured to select, for a group of subcarriers, one of the first frequency transformation circuit and the second frequency transformation circuit, and cause, for the group of subcarriers, the selected frequency transformation circuit to output one of the second signal and the fourth signal, according to the selection.

Abstract: In some aspects, the disclosure is directed to methods and systems for improving signal to noise ratios of signals from multiple communication links. In some embodiments, a system includes a first frequency transformation circuit configured to transform a first signal in a time domain received from a first device into a corresponding second signal in a frequency domain. The system further includes a second frequency transformation circuit configured to transform a third signal in the time domain received from a second device into a corresponding fourth signal in the frequency domain. The system further includes a leg combining circuit configured to select, for a group of subcarriers, one of the first frequency transformation circuit and the second frequency transformation circuit, and cause, for the group of subcarriers, the selected frequency transformation circuit to output one of the second signal and the fourth signal, according to the selection.

Abstract: A communication device (device) includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other device(s) and to generate and process signals for such communications. The device receives a ranging instruction signal, which includes an initial power and at least one power step, from another device. The device processes the ranging instruction generates a first ranging signal based on the initial power. The device then transmits the first ranging signal to the another device. When a ranging response to the first ranging signal is received from the another device, the device determines that the device is successfully ranged to the another device. Alternatively, when no ranging response is received, the device generates a second ranging signal based on the initial power and the at least one power step and transmit the second ranging signal to the another device.

Abstract: A method and system for generating a data frame in an upstream frame in an Ethernet Passive Optical Network protocol over Coax (EPoC) network is provided. The data frame includes a plurality of resource blocks, each of a particular type. The resource blocks are arranged in the data frame in accordance with pilot rules and a pilot pattern.

Abstract: The present disclosure is directed to a system and method for detecting burst noise. The system and method are described in the exemplary context of a cable modem system and can be used in such a system to specifically detect upstream burst noise. Once detected, the system and method can adjust the upstream receiver that receives data corrupted by the upstream burst noise to reduce the potentially deleterious effects that the burst noise can have on, for example, the packet error rate and/or data rate of the upstream receiver.

Abstract: Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC). Adaptive processing is performed on a signal based on one or more effects which may deleteriously modify a signal. For example, based on a modification of a signal to noise ratio (SNR) associated with one or more impulse or burst noise events, which may be estimated, different respective processing may be performed selectively to differently affected bits associated with the signal. For example, two respective SNRs may be employed: a first SNR for one or more first bits, and a second SNR for one or more second bits. For example, as an impulse or burst noise event may affect different respective bits of a codeword differently, and adaptive processing may be made such that different respective bits of the codeword may be handled differently.

Abstract: A communication device (device) includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other device(s) and to generate and process signals for such communications. The device receives a ranging instruction signal, which includes an initial power and at least one power step, from another device. The device processes the ranging instruction generates a first ranging signal based on the initial power. The device then transmits the first ranging signal to the another device. When a ranging response to the first ranging signal is received from the another device, the device determines that the device is successfully ranged to the another device. Alternatively, when no ranging response is received, the device generates a second ranging signal based on the initial power and the at least one power step and transmit the second ranging signal to the another device.

Abstract: The present disclosure is directed to an apparatus and method for processing data for upstream transmission. The apparatus and method can be implemented within a cable modem to specifically process data for upstream transmission over a hybrid fiber coaxial (HFC) network to a cable modem termination system in accordance with parameters in an upstream profile. The upstream profile can be specified by the cable modem termination system.

Abstract: A method and system for generating a data frame in an upstream frame in an Ethernet Passive Optical Network protocol over Coax (EPoC) network is provided. The data frame includes a plurality of resource blocks, each of a particular type. The resource blocks are arranged in the data frame in accordance with pilot rules and a pilot pattern.

Abstract: Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC). Adaptive processing is performed on a signal based on one or more effects which may deleteriously modify a signal. For example, based on a modification of a signal to noise ratio (SNR) associated with one or more impulse or burst noise events, which may be estimated, different respective processing may be performed selectively to differently affected bits associated with the signal. For example, two respective SNRs may be employed: a first SNR for one or more first bits, and a second SNR for one or more second bits. For example, as an impulse or burst noise event may affect different respective bits of a codeword differently, and adaptive processing may be made such that different respective bits of the codeword may be handled differently.

Abstract: The present disclosure is directed to a system and method for detecting burst noise. The system and method are described in the exemplary context of a cable modem system and can be used in such a system to specifically detect upstream burst noise. Once detected, the system and method can adjust the upstream receiver that receives data corrupted by the upstream burst noise to reduce the potentially deleterious effects that the burst noise can have on, for example, the packet error rate and/or data rate of the upstream receiver.

Abstract: Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.

Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

Abstract: Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.

Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.