Patents by Inventor Anatoly Belous

Anatoly Belous has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating gate inverter type memory cell and array
    Patent number: 8378407
    Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: February 19, 2013
    Assignee: Tower Semiconductor, Ltd.
    Inventors: Mikalai Audzeyeu, Yuriy Makarevich, Siarhei Shvedau, Anatoly Belous, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
  • Floating Gate Inverter Type Memory Cell And Array
    Publication number: 20100157669
    Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Applicant: Tower Semiconductor Ltd.
    Inventors: Mikalai Audzeyeu, Yuriy Makarevich, Siarhei Shvedau, Anatoly Belous, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin