Abstract: Some embodiments provide a multi-phase DC/DC switching converter in which each of the phases are controlled using a common comparator for comparing an output voltage of the switching converter and a reference voltage, with in some embodiments each of the phases including a bypass switch for coupling ends of an output inductor of the switching converter. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases are operated with clock signals having frequencies different than clock signals used for operating others of the phases. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases include inductors having inductances different than inductances for inductors of others of the phases.

Abstract: Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.

Abstract: Circuitry may monitor a processor supply voltage and pull power from the processor supply on a temporary basis when the supply voltage rises above predetermined levels. In some embodiments this may be done without explicit knowledge of a commanded supply voltage level for the processor.

Abstract: Some embodiments provide a multi-phase DC/DC switching converter in which each of the phases are controlled using a common comparator for comparing an output voltage of the switching converter and a reference voltage, with in some embodiments each of the phases including a bypass switch for coupling ends of an output inductor of the switching converter. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases are operated with clock signals having frequencies different than clock signals used for operating others of the phases. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases include inductors having inductances different than inductances for inductors of others of the phases.

Abstract: Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.

Abstract: Systems and methods for changing an output voltage of a voltage regulator are disclosed. A voltage change command that is serially transmitted from a control system to a voltage regulator is used to indicate that a change is output voltage is requested. The voltage change command is a serial stream that is less than a byte in length and includes a 1-bit write operation field, a 1-bit voltage change field and up to 6 bits of voltage change information.

Abstract: Design of a power delivery network (PDN) is integrated with a digital logic design flow.

Abstract: Design of a power delivery network (PDN) is integrated with a digital logic design flow.

Abstract: Circuitry may monitor a processor supply voltage and pull power from the processor supply on a temporary basis when the supply voltage rises above predetermined levels. In some embodiments this may be done without explicit knowledge of a commanded supply voltage level for the processor.

Abstract: Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.

Abstract: Systems and methods for changing an output voltage of a voltage regulator are disclosed. A voltage change command that is serially transmitted from a control system to a voltage regulator is used to indicate that a change is output voltage is requested. The voltage change command is a serial stream that is less than a byte in length and includes a 1-bit write operation field, a 1-bit voltage change field and up to 6 bits of voltage change information.

Abstract: Systems and methods for providing an indication of an output current of a voltage regulator applied to a load at an indicated time to a processor. An indication of the output current of a voltage regulator is determined in response to a clock signal received from a clock source and a frame number of a frame is determined from the clock source. The indication of the current output and the frame number of the associated frame are provided to the processor.

Abstract: Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.

Abstract: A voltage regulator and/or associated circuitry provides an indication of average current consumed or drawn by a load, level and magnitude of transient events, and regulation efficiency. A dynamic voltage and frequency scaling governor makes use of the indication of average current consumed or drawn by the load, level and magnitude of transient events, and regulation efficiency to help optimize operation of the load, with respect to power and/or performance.

Abstract: Design of a power delivery network (PDN) is integrated with a digital logic design flow.

Abstract: A voltage regulator and/or associated circuitry provides an indication of average current consumed or drawn by a load, level and magnitude of transient events, and regulation efficiency. A dynamic voltage and frequency scaling governor makes use of the indication of average current consumed or drawn by the load, level and magnitude of transient events, and regulation efficiency to help optimize operation of the load, with respect to power and/or performance.

Abstract: A voltage regulator and/or associated circuitry provides an indication of average current consumed or drawn by a load, level and magnitude of transient events, and regulation efficiency. A dynamic voltage and frequency scaling governor makes use of the indication of average current consumed or drawn by the load, level and magnitude of transient events, and regulation efficiency to help optimize operation of the load, with respect to power and/or performance.

Abstract: Separate power island for high performance processor. A multi-processor design is presented in which each of the processors is implemented in separately powered portions of a circuitry (e.g., an integrated circuit). One of the processors can be a main application processor, and another of the processors can be a baseband processor. In addition, the each of the processors can be implemented using different types of circuitry (e.g., one of the processors [such as the main application processor] is implemented using higher performance/higher leakage circuitry that another of the processors [such as the baseband processor]). One of the processors (e.g., main application processor) can be powered down when not needed thereby providing energy/power conservation which can be vital is handheld communication device applications such as wireless handheld communication devices.

Abstract: Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be.

Abstract: Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.