Abstract: A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit") does not. The result of the rounding subunit is selected as the addition result when one of the following conditions (R1), (R2), (R3) is true: (R1) the operation is an effective addition; (R2) the operation is an effective subtraction, the magnitude ED of the difference between the exponents of the operands is 1, and normalization of the result is not required; (R3) the operation is an effective subtraction and ED>1. The addition result is selected from the non-rounding subunit in the remaining cases. In some embodiments, the rounding subunit overlaps rounding with adding the operands, significands. In some embodiments, the addition unit satisfies ANSI/IEEE Standard 754-1985.

Abstract: A leading 0/1 anticipator (LZA) generates a signal representing the exact number of leading non-significant binary digits in the significand of the result of an addition of two floating point numbers. The exact number is provided because the LZA takes into account all the carries of the addition operation providing the significand of the result. The signal generated by the LZA is used for normalization as a shift amount by which the significand of the result is shifted. The signal is generated as a binary number, that is, as a plurality of binary signals each of which represents one binary digit of the number of the leading non-significant digits. In some floating point addition operations, the LZA receives a signal representing a maximum value of the number of non-significant digits that can be eliminated. The shift amount generated by the LZA does not exceed this maximum value. Taking into account the maximum value does not create an additional delay.