Abstract: A clock relationship based re-convergence analysis method includes receiving, by a processing device, a register-transfer level (RTL) description of a design relating to an integrated circuit (IC). The method further includes identifying one or more clock domain crossing (CDC) synchronizers in the RTL description of the design, and generating a levelized topological abstract graph (LTAG) including a network of nodes. Each node includes a CDC synchronizer. The method further includes traversing the LTAG starting from a first output of the one or more CDC synchronizers, and responsive to determining that a first CDC synchronizer of the one or more CDC synchronizers is converging with a second CDC synchronizer, identifying a first potential convergence violation associated with the first CDC synchronizer and the second CDC synchronizer.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.