Patents by Inventor Anda C. Mocuta
Anda C. Mocuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7705345Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.Type: GrantFiled: January 7, 2004Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu, Anthony G. Domenicucci, Kam-Leung Lee, Anda C. Mocuta, John A. Ott, Qiqing C. Ouyang
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Patent number: 7691698Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.Type: GrantFiled: February 21, 2006Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Anda C. Mocuta, Dan M. Mocuta, Carl Radens
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Patent number: 7655557Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: June 24, 2008Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20090179269Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.Type: ApplicationFiled: December 22, 2008Publication date: July 16, 2009Inventors: Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight, Anthony K. Stamper
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Patent number: 7560326Abstract: A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.Type: GrantFiled: May 5, 2006Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Dureseti Chidambarrao, Ricardo A. Donaton, David M. Onsongo, Kern Rim
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Publication number: 20090106714Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 7492016Abstract: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.Type: GrantFiled: March 31, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight, Anthony K. Stamper
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Publication number: 20080254622Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: June 24, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7411227Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: April 19, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20080179680Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.Type: ApplicationFiled: March 25, 2008Publication date: July 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti CHIDAMBARRAO, Anda C. Mocuta, Dan M. Mocuta, Carl Radens
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Publication number: 20080179636Abstract: The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.Type: ApplicationFiled: January 27, 2007Publication date: July 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti Chidambarrao, Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta, David M. Onsongo, Carl J. Radens
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Patent number: 7268049Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.Type: GrantFiled: September 30, 2004Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Huilong Zhu, Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta
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Patent number: 7067400Abstract: A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.Type: GrantFiled: September 17, 2004Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Anda C. Mocuta
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Patent number: 7056782Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: February 25, 2004Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaran Surendra
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Patent number: 6916698Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: March 8, 2004Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Patent number: 6881635Abstract: A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.Type: GrantFiled: March 23, 2004Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Effendi Leobandung, Anda C. Mocuta, Haining S. Yang, Huilong Zhu
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Publication number: 20040171205Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: ApplicationFiled: March 8, 2004Publication date: September 2, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Patent number: 6762469Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: April 19, 2002Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Patent number: 6746924Abstract: A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor.Type: GrantFiled: February 27, 2003Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Byoung H. Lee, Anda C. Mocuta
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Publication number: 20030197230Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: ApplicationFiled: April 19, 2002Publication date: October 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen