Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming a dual damascene interconnect structure, by use of the present invention, a planar topography of the BARC layer is achieved by chemical mechanical polishing. The present invention applies a low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of the BARC layer is provided before coating the photoresist, so formation of the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on the via and the critical dimension control for the via are improved by patterning the via on a planar and an anti-reflective surface.

Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming dual damascene interconnect structure, by use of the present invention, a planar topography of BARC layer is achieved by chemical mechanical polishing. The present invention applies low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of BARC layer is provided before coating the photoresist, so the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on via and the critical dimension control for via are improved by patterning via on a planar and anti-reflective surface.

Abstract: A lithography process for producing gates and connections thereof, which can reduce the pitch of gate end connections is provided. The process comprises the steps of forming a photoresist layer on the substrate; exposing the photoresist layer by using a phase shifter mask to form a gates pattern in the photoresist layer in the device region; exposing the photoresist layer by using a trimming mask to form a conductive lines pattern connected to the gates pattern in the photoresist layer in the isolation region; and developing the photoresist layer.

Abstract: The invention provides a lithography process for forming openings. The method comprises forming a negative photoresist layer. A first mask is used to transfer a first strip pattern to the negative photoresist layer, so that a plurality of first strips, parallel to each other, are formed. A second mask is used to transfer a second strip pattern to the negative photoresist layer, forming a plurality of second strips, parallel to each other. Because the second strip pattern is perpendicular to the first strip pattern, the combined exposure of these two patterns forms a plurality of opening patterns. A trim mask is used to transfer a pattern to the negative photoresist layer for shielding the opening patterns in specific regions and exposing the opening patterns outside the specific regions to light. The negative photoresist layer is then developed.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.