Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: A method for establishing a powered link over a transmission line includes providing a constant, predetermined current to a terminal thereby causing a power transistor coupled to the terminal to conduct in a subthreshold region of transistor operation without current flowing between a drain terminal of the power transistor and a source terminal of the power transistor. The method includes estimating a size of the power transistor using a digital time signal indicative of an amount of time the constant, predetermined current is provided before a voltage level on the terminal exceeds a predetermined voltage level. In an embodiment, the predetermined voltage level is less than a threshold voltage of the power transistor.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: A method for establishing a powered link over a transmission line includes providing a constant, predetermined current to a terminal thereby causing a power transistor coupled to the terminal to conduct in a subthreshold region of transistor operation without current flowing between a drain terminal of the power transistor and a source terminal of the power transistor. The method includes estimating a size of the power transistor using a digital time signal indicative of an amount of time the constant, predetermined current is provided before a voltage level on the terminal exceeds a predetermined voltage level. In an embodiment, the predetermined voltage level is less than a threshold voltage of the power transistor.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: A method for establishing a powered link over a transmission line includes enabling a current source to provide a constant, predetermined current to a terminal. The method includes sensing a voltage on the terminal to generate a sensed voltage level. The method includes comparing the sensed voltage level on the terminal to a predetermined voltage level. The method includes disabling the current source in response to the sensed voltage level equaling or exceeding the predetermined voltage level. The method may include, while the current source is enabled, a power transistor coupled to the terminal is disabled and only conducts current in a subthreshold region of transistor operation.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.