Patents by Inventor Andras Vajda

Andras Vajda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10178017
    Abstract: A method and a control node (300) for establishing network functions for processing data packets of a data flow from a delivering node (306) to a receiving node (308) over a communication network (302). The control node identifies (3:2) flow characteristics relating to the data flow and determines (3:3) a succession of network functions (304) in the network for processing the data packets, based on the identified flow characteristics. The network functions (304) are then instructed (3:4a-c) to forward the data packets in the data flow according to the determined succession. The sequence of network functions specifies a service chain. The controller uses OpenFlow. Network functions are dynamically relocated based on network conditions.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 8, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Ignacio Más Ivars, Andras Vajda
  • Patent number: 9619301
    Abstract: A method of operating a multi-core processor. In one embodiment, each processor core is provided with its own private cache and the device comprises or has access to a common memory, and the method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and comprising allocating sole responsibility for writing data to given blocks of said common memory, to respective processor cores. The method further comprises implementing a speculative execution mode switchable to override said normal access mode. This speculative execution mode comprises, upon identification of said operation within said processing thread, transferring responsibility for performing said operation to a plurality of second processor cores, and optionally performing said operation on the first processor core as well.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: April 11, 2017
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Andras Vajda, Per Stenström
  • Publication number: 20160344611
    Abstract: A method and a control node (300) for establishing network functions for processing data packets of a data flow from a delivering node (306) to a receiving node (308) over a communication network (302). The control node identifies (3:2)flow characteristics relating to the data flow and determines (3:3) a succession of network functions (304) in the network for processing the data packets, based on the identified flow characteristics. The network functions (304) are then instructed (3:4a-c) to forward the data packets in the data flow according to the determined succession. The sequence of network functions specifies a service chain. The controller uses OpenFlow. Network functions are dynamically relocated based on network conditions.
    Type: Application
    Filed: December 18, 2013
    Publication date: November 24, 2016
    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Ignacio MÁS IVARS, Andras VAJDA
  • Patent number: 8984523
    Abstract: Method and scheduler in an operating system, for scheduling processing resources on a multi-core chip. The multi-core chip comprises a plurality of processor cores. The operating system is configured to schedule processing resources to an application to be executed on the multi-core chip. The method comprises allocating a plurality of processor cores to the application. Also, the method comprises switching off another processor core allocated to the application, not executing the sequential portion of the application, when a sequential portion of the application is executing on only one processor core. In addition, the method comprises increasing the frequency of the one processor core executing the application to the second frequency, such that the processing speed is increased more than predicted by Amdahl's law.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: March 17, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Andras Vajda
  • Publication number: 20140033217
    Abstract: A method of operating a multi-core processor. In one embodiment, each processor core is provided with its own private cache and the device comprises or has access to a common memory, and the method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and comprising allocating sole responsibility for writing data to given blocks of said common memory, to respective processor cores. The method further comprises implementing a speculative execution mode switchable to override said normal access mode. This speculative execution mode comprises, upon identification of said operation within said processing thread, transferring responsibility for performing said operation to a plurality of second processor cores, and optionally performing said operation on the first processor core as well.
    Type: Application
    Filed: April 5, 2012
    Publication date: January 30, 2014
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Andras Vajda, Per Stenström
  • Publication number: 20120060170
    Abstract: Method and scheduler in an operating system, for scheduling processing resources on a multi-core chip. The multi-core chip comprises a plurality of processor cores. The operating system is configured to schedule processing resources to an application to be executed on the multi-core chip. The method comprises allocating a plurality of processor cores to the application. Also, the method comprises switching off another processor core allocated to the application, not executing the sequential portion of the application, when a sequential portion of the application is executing on only one processor core. In addition, the method comprises increasing the frequency of the one processor core executing the application to the second frequency, such that the processing speed is increased more than predicted by Amdahl's law.
    Type: Application
    Filed: May 26, 2009
    Publication date: March 8, 2012
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Andras Vajda
  • Publication number: 20110113221
    Abstract: System, computer readable medium and method for providing transparent access to shared data (16) in a chip multi-processor system (900), without using locks or transactional memory constructs, where a first set of processing entities (12) communicate with a second set of processing entities (14) via a task queue (20) for executing a code that necessitates access to the shared data (16).
    Type: Application
    Filed: August 18, 2008
    Publication date: May 12, 2011
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventor: Andras Vajda