Patents by Inventor Andre Klindworth
Andre Klindworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10915321Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: GrantFiled: August 20, 2018Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Patent number: 10860482Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: February 11, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20190171567Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 10223263Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: December 28, 2017Date of Patent: March 5, 2019Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 10067764Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: GrantFiled: July 11, 2017Date of Patent: September 4, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Publication number: 20180121356Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 9928171Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: June 29, 2017Date of Patent: March 27, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20170308382Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Publication number: 20170300413Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: June 29, 2017Publication date: October 19, 2017Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 9740485Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: GrantFiled: March 15, 2013Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Patent number: 9727493Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: August 14, 2013Date of Patent: August 8, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20150052299Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Applicant: Micron Technology, Inc.Inventors: GRAZIANO MIRICHIGNI, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20140122814Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: ApplicationFiled: March 15, 2013Publication date: May 1, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Patent number: 6771701Abstract: A configurable adaptive filter that is used for echo cancellation is disclosed, which includes a method of detecting a voice or no-voice signal. The presence of a voice or no-voice signal is determined by calculating a histogram of signal amplitude value over a period of time. If this histogram has more than a predefined number of samples that are above a threshold then the signal is classified as no-voice or periodic otherwise the signal is classified as a voice signal. A variable maximum amplitude limit and lower amplitude thresholds are disclosed to detect a voice or no-voice from the histogram signal faster than traditional methods utilized in echo cancelers. A configurable hysteresis time is used to ensure the signal register primarily contains voice signal when the filter coefficients of the echo canceler are allowed to adapt.Type: GrantFiled: December 29, 1999Date of Patent: August 3, 2004Assignee: Infineon Technologies North America CorporationInventors: Andre Klindworth, Erik Hogl, Ulrich Fiedler
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Patent number: 6535048Abstract: A system and method for clock multiplexing. According to one implementation, a pair of two stage cross-coupled clock gating elements are controlled by a single asynchronous enable signal. On change of the enable signal, the previously selected clock gets disabled before the newly selected clock is enabled.Type: GrantFiled: February 8, 2000Date of Patent: March 18, 2003Assignee: Infineon Technologies North America Corp.Inventor: Andre Klindworth