Patents by Inventor Andre M. Martinez

Andre M. Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5541120
    Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filler with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optical cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: July 30, 1996
    Assignee: Analog Devices, Inc.
    Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt
  • Patent number: 5444285
    Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: August 22, 1995
    Assignee: Analog Devices, Inc.
    Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt
  • Patent number: 5409845
    Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: April 25, 1995
    Assignee: Analog Devices, Inc.
    Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt
  • Patent number: 4795679
    Abstract: A capped recrystallizable silicon layer covering a substrate is provided with a thin buffer layer between the capping layer and the silicon layer. This recrystallizable silicon layer is then converted to a monocrystalline silicon layer.
    Type: Grant
    Filed: April 23, 1987
    Date of Patent: January 3, 1989
    Assignee: North American Philips Corporation
    Inventors: Subramanian Ramesh, Andre M. Martinez
  • Patent number: 4743567
    Abstract: A structure comprising thin defect-free monocrystalline layer of a silicon of an insulating layer is produced from a structure comprising a thin recrystallizable layer of silicon on an insulating layer by use of a low softening point insulating layer, scanning the structure relative to a zone heater the beams of which are focused on the recrystallizable silicon layer so as to form a melt zone having a convex solid-liquid interface in the silicon layer while forming a liquid area under the melt zone in the insulating layer.
    Type: Grant
    Filed: August 11, 1987
    Date of Patent: May 10, 1988
    Assignee: North American Philips Corp.
    Inventors: Ranjana Pandya, Andre M. Martinez