Abstract: A circuit includes a first feedforward path configured to determine a state of a first power switch using a first gate control voltage from a gate driver and a source voltage of the first power switch, and to apply a gate driving voltage to a gate of the first power switch based on the determined state of the first power switch; and a first feedback path configured to provide a scaled value of a drain voltage of the first power switch and a scaled value of the source voltage of the first power switch to the gate driver, where the first feedforward path and the first feedback path are configured to provide a bi-directional gate interface coupled between the gate driver and the first power switch.

Abstract: A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected.

Abstract: A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected.

Abstract: A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected.

Abstract: According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example.

Abstract: A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.

Abstract: According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: A method of driving a power transistor switch comprising: receiving a drive input signal; converting the drive input signal into a converted drive input signal; and providing the converted gate drive input signal to a control electrode of the switch to turn on the switch, the converted drive input signal having three regions with respect to time, each having a slope, a first region in time having a first slope up to a Miller Plateau of the switch; a second region in time having a second slope with a reduced slope compared with the first slope; and a third region having a third slope that is greater than the second slope, whereby the control electrode voltage rapidly reaches the Miller Plateau voltage, then more slowly reaches a threshold voltage of the switch and then, when the switch has substantially fully turned on, the control electrode voltage is rapidly increased. The switch delay time is also maintained substantially constant by adjusting the transistor control electrode precharge voltage.

Abstract: A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.

Abstract: A circuit for converting a duty cycle of a pulse width modulated signal to an analog value comprising a clock signal generator for generating a clock signal, a window generation circuit for generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination, a counter drive circuit receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal, a counter circuit for counting pulses of the counter input signal and providing a counter output, a reset circuit for resetting the counter at the termination of the window; and a digital to analog converter for converting the counter output at the termination of the window to the analog value.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: A method of driving a power transistor switch comprising: receiving a drive input signal; converting the drive input signal into a converted drive input signal; and providing the converted gate drive input signal to a control electrode of the switch to turn on the switch, the converted drive input signal having three regions with respect to time, each having a slope, a first region in time having a first slope up to a Miller Plateau of the switch; a second region in time having a second slope with a reduced slope compared with the first slope; and a third region having a third slope that is greater than the second slope, whereby the control electrode voltage rapidly reaches the Miller Plateau voltage, then more slowly reaches a threshold voltage of the switch and then, when the switch has substantially fully turned on, the control electrode voltage is rapidly increased. The switch delay time is also maintained substantially constant by adjusting the transistor control electrode precharge voltage.

Abstract: A motor drive comprising a first power semiconductor switching device having a pair of main current carrying terminals, the main current carrying terminals being coupled in series with a motor load; a first current control loop, the current control loop having a current sensor for the switching device for controlling the current through the switching device; a current limiting circuit driving the first current control loop to maintain the current in the switching device at a desired level, the current limiting circuit having first and second inputs; a speed regulation circuit having a first input coupled to a speed control input and a second input coupled to a feedback voltage from the motor representing the actual motor speed, the speed regulation circuit providing an output to the first input of the current limiting circuit to drive the motor to the desired motor speed; and a power limitation circuit for limiting the power consumed by the motor to a predetermined level and providing an output to the second

Abstract: A motor drive comprising a first power semiconductor switching device having a pair of main current carrying terminals, the main current carrying terminals being coupled in series with a motor load; a first current control loop, the current control loop having a current sensor for the switching device for controlling the current through the switching device; a current limiting circuit driving the first current control loop to maintain the current in the switching device at a desired level, the current limiting circuit having first and second inputs; a speed regulation circuit having a first input coupled to a speed control input and a second input coupled to a feedback voltage from the motor representing the actual motor speed, the speed regulation circuit providing an output to the first input of the current limiting circuit to drive the motor to the desired motor speed; and a power limitation circuit for limiting the power consumed by the motor to a predetermined level and providing an output to the second

Abstract: A circuit for converting a duty cycle of a pulse width modulated signal to an analog value comprising a clock signal generator for generating a clock signal, a window generation circuit for generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination, a counter drive circuit receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal, a counter circuit for counting pulses of the counter input signal and providing a counter output, a reset circuit for resetting the counter at the termination of the window; and a digital to analog converter for converting the counter output at the termination of the window to the analog value.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.