Patents by Inventor Andre Schmenn
Andre Schmenn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929305Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.Type: GrantFiled: November 22, 2021Date of Patent: March 12, 2024Assignee: Infineon Technologies AGInventors: Andre Schmenn, Klaus Diefenbeck, Joost Adriaan Willemen
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Patent number: 11916059Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: GrantFiled: August 25, 2021Date of Patent: February 27, 2024Assignee: Infineon Technologies AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Publication number: 20230307388Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Inventors: Andre Schmenn, Isabella Goetz, Egle Tylaite
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Patent number: 11600615Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.Type: GrantFiled: July 2, 2020Date of Patent: March 7, 2023Assignee: Infineon Technologies AGInventors: Vadim Valentinovic Vendt, Joost Adriaan Willemen, Andre Schmenn, Damian Sojka
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Publication number: 20220165646Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.Type: ApplicationFiled: November 22, 2021Publication date: May 26, 2022Inventors: Andre Schmenn, Klaus Diefenbeck, Joost Adriaan Willemen
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Publication number: 20220045046Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: ApplicationFiled: August 25, 2021Publication date: February 10, 2022Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 11127733Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: GrantFiled: February 6, 2020Date of Patent: September 21, 2021Assignee: Infineon Technologies AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Publication number: 20200335494Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventors: Vadim Valentinovic Vendt, Joost Adriaan Willemen, Andre Schmenn, Damian Sojka
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Patent number: 10741548Abstract: A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.Type: GrantFiled: August 4, 2015Date of Patent: August 11, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Vadim Valentinovic Vendt, Joost Willemen, Andre Schmenn, Damian Sojka
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Publication number: 20200176438Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 10672758Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.Type: GrantFiled: October 18, 2017Date of Patent: June 2, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Vadim Valentinovic Vendt, Stefan Pompl, Andre Schmenn, Joost Willemen
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Patent number: 10622346Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remainType: GrantFiled: September 29, 2017Date of Patent: April 14, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Patent number: 10593615Abstract: A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.Type: GrantFiled: May 3, 2018Date of Patent: March 17, 2020Assignee: Infineon Technologies AGInventors: Andre Schmenn, Damian Sojka
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Patent number: 10504772Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.Type: GrantFiled: June 22, 2017Date of Patent: December 10, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Alfons Dehe, Damian Sojka, Andre Schmenn, Carsten Ahrens
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Patent number: 10153266Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.Type: GrantFiled: September 22, 2016Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Thomas Fischer, Carsten Ahrens, Damian Sojka, Andre Schmenn
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Publication number: 20180323136Abstract: A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.Type: ApplicationFiled: May 3, 2018Publication date: November 8, 2018Applicant: Infineon Technologies AGInventors: Andre Schmenn, Damian Sojka
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Patent number: 9966277Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.Type: GrantFiled: November 25, 2016Date of Patent: May 8, 2018Assignee: Infineon Technologies AGInventors: Markus Zundel, Andre Schmenn, Damian Sojka, Isabella Goetz, Gudrun Stranzl, Sebastian Werner, Thomas Fischer, Carsten Ahrens, Edward Fuergut
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Publication number: 20180108648Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.Type: ApplicationFiled: October 18, 2017Publication date: April 19, 2018Inventors: Vadim Valentinovic Vendt, Stefan Pompl, Andre Schmenn, Joost Willemen
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Publication number: 20180096984Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remainType: ApplicationFiled: September 29, 2017Publication date: April 5, 2018Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 9911822Abstract: A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.Type: GrantFiled: October 28, 2016Date of Patent: March 6, 2018Assignee: Infineon Technologies AGInventors: Andre Schmenn, Damian Sojka