Abstract: A process for treating waste waters with TDS?20 g/l, possibly containing organic substances, includes the following steps: a. separating the saline wastewater or waste waters from suspended solids and heavy pollutants by physical separation, forming a saline stream free of suspended solids and heavy pollutants; b. subjecting the saline stream to reverse electro-dialysis, using a reservoir solution to reduce the saline concentration and forming a diluate and a diluted stream (waste water) with TDS not higher than 20 g/l; and c. biologically treating the diluted stream obtained in (b) forming biological sludge, or excess sludge, and clarified water.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one regulation signal indicative of a result of said comparison, wherein said regulation signal is fed to the oscillator to control said oscillation frequency. The regulation circuit is adapted to cause the at least one regulation signal take one among a plurality of discrete values, depending on the result of the comparison, so that the oscillation frequency of the at least one periodical signal accordingly can take one among a plurality of discrete oscillation frequency values.

Abstract: A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one regulation signal indicative of a result of said comparison, wherein said regulation signal is fed to the oscillator to control said oscillation frequency. The regulation circuit is adapted to cause the at least one regulation signal take one among a plurality of discrete values, depending on the result of the comparison, so that the oscillation frequency of the at least one periodical signal accordingly can take one among a plurality of discrete oscillation frequency values.