Patents by Inventor Andrea Cenciotti

Andrea Cenciotti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8566380
    Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: October 22, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Andrea Cenciotti, Nestor Lucas Barriola, Philip John Young
  • Publication number: 20100306298
    Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.
    Type: Application
    Filed: May 15, 2008
    Publication date: December 2, 2010
    Applicant: Qualcomm Incorporated
    Inventors: Andrea Cenciotti, Nestor Lucas Barriola, Philip John Young
  • Patent number: 6724823
    Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: April 20, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabrizio Rovati, Danilo Pau, Luca Fanucci, Sergio Saponara, Andrea Cenciotti, Daniele Alfonso
  • Publication number: 20020097343
    Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.
    Type: Application
    Filed: September 6, 2001
    Publication date: July 25, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fabrizio Rovati, Danilo Pau, Luca Panucci, Sergio Saponara, Andrea Cenciotti, Daniele Alfonso