Patents by Inventor Andrea Pozzato
Andrea Pozzato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11763908Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 13, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
-
Patent number: 11670342Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.Type: GrantFiled: December 24, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Publication number: 20220189513Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.Type: ApplicationFiled: December 24, 2021Publication date: June 16, 2022Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Publication number: 20220101938Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
-
Patent number: 11211100Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: GrantFiled: December 15, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Patent number: 11211136Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: June 26, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
-
Publication number: 20210098030Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Publication number: 20200411129Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
-
Patent number: 10872639Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: GrantFiled: August 29, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Publication number: 20200211603Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: ApplicationFiled: August 29, 2019Publication date: July 2, 2020Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
-
Patent number: 6940756Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.Type: GrantFiled: December 18, 2003Date of Patent: September 6, 2005Assignee: STMicroelectronics S.r.l.Inventors: Francesco Mastroianni, Massimiliano Scotti, Antonio Geraci, Andrea Pozzato
-
Publication number: 20040165434Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.Type: ApplicationFiled: December 18, 2003Publication date: August 26, 2004Applicant: STMicroelectronics S.r.I.Inventors: Francesco Mastroianni, Massimiliano Scotti, Antonio Geraci, Andrea Pozzato