Abstract: A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.

Abstract: A Chemical Mechanical Polishing, CMP, process applied to a wafer of Silicon Carbide having a thickness of, or lower than, 200 ?m, comprising the steps of: arranging the wafer on a supporting head of a CMP processing apparatus, the wafer having a front side and a back side opposite to one another, the front side housing at least one electronic component and being coupled to the supporting head; deliver a polishing slurry on the wafer, wherein the polishing slurry has a pH in the range 2-3; pressing the back side of the wafer against a polishing pad of the CMP apparatus exerting, by the supporting head, a pressure on the polishing pad in the range 5-20 kPa; setting a rotation of the polishing pad in the range 30-180 rpm, and setting a rotation of polishing head in the range 30-180 rpm; setting and maintaining a CMP process temperature equal to, or below, 50° C.

Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon (205); on the starting wafer of crystalline silicon, epitaxially growing a buffer layer (210) consisting of a sub-stoichiometric alloy of silicon and germanium; epitaxially growing on the buffer layer a layer (225) of a semiconductor material having an energy gap greater than that of the crystalline silicon constituting the starting wafer, wherein the layer of semiconductor material having an energy gap greater than that of the crystalline silicon is grown so to have a thickness capable of constituting a substrate for the integration therein of electronic and/or optical and/or optoelectronic devices.