Patents by Inventor Andreas Augustin
Andreas Augustin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240108404Abstract: A technique of renal denervation comprising methods and devices for generating one or more bubbles to at least partially fragment a calcification of a calcified region of a renal artery and for ablating one or more nerves about, within, or surrounding the calcified region of the renal artery after the calcification has been at least partially fragmented. Other embodiments are described and claimed.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Inventors: Andrew Weiss, Liang Zhai, Dimitri Augustin, Andrea Methven
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Publication number: 20240097727Abstract: An electronic device may be provided with an antenna, a receiver, and baseband circuitry coupled to the receiver over a digital interface. The receiver may receive radio-frequency signals using the antenna and may generate digital in-phase and quadrature-phase (I/Q) samples from the radio-frequency signals. The I/Q samples may have a bit width and may be transmitted to the baseband circuitry over the digital interface. The baseband circuitry may evaluate a radio condition of the receiver based on the I/Q samples. The baseband circuitry may adjust the bit width of the I/Q samples based on the radio condition. For example, the baseband circuitry may decrease the bit width when wireless performance metric data falls below a threshold and/or may increase the bit width when the wireless performance metric data exceeds a threshold. This may minimize power consumed by the digital interface without sacrificing wireless performance.Type: ApplicationFiled: September 15, 2023Publication date: March 21, 2024Inventors: Thomas Hauser, Joachim Wehinger, Michael Weber, Andreas Augustin
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Publication number: 20240084516Abstract: An under sleeper pad (1) for fastening to an outer surface (2) facing a ballast bed (16), in particular an underside, of a railroad sleeper (3). The under sleeper pad (1) includes an elastomer layer (5), the elastomer layer (5) having a density in the range of 250 kg/m3 to 350 kg/m3, preferably 250 kg/m3 to 330 kg/m3.Type: ApplicationFiled: September 7, 2023Publication date: March 14, 2024Applicant: Getzner Werkstoffe Holding GmbHInventors: Andreas Augustin, Stefan Kopeinig, Harald Loy, Martin Quirchmair
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Patent number: 11784143Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: GrantFiled: May 23, 2019Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Sonja Koller, Kilian Roth, Josef Hagn, Andreas Wolter, Andreas Augustin
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Patent number: 11764187Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.Type: GrantFiled: September 29, 2017Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
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Patent number: 11646498Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: GrantFiled: May 16, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Kilian Roth, Sonja Koller, Josef Hagn, Andreas Wolter, Andreas Augustin
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Patent number: 11521793Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: GrantFiled: December 15, 2020Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Patent number: 11456116Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.Type: GrantFiled: March 30, 2017Date of Patent: September 27, 2022Assignee: Intel CorporationInventors: Andreas Augustin, Bernd Waidhas, Sonja Koller, Reinhard Mahnkopf, Georg Seidemann
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Publication number: 20220294115Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoecki, Thomas Wagner, Josef Hagn
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Patent number: 11374323Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.Type: GrantFiled: March 31, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
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Patent number: 11127813Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.Type: GrantFiled: June 30, 2017Date of Patent: September 21, 2021Assignee: Intel CorporationInventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Andreas Augustin
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Publication number: 20210273342Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
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Publication number: 20210212491Abstract: An under sleeper pad (1) to be fastened to an underside (3) of a sleeper (4), on the opposite side from the tracks (2). The under sleeper pad (1) has at least one elastic layer (5) having cork grains (6) of a cork granulate distributed throughout. In addition, the elastic layer (5) has at least one cellular synthetic elastomer (7).Type: ApplicationFiled: January 17, 2019Publication date: July 15, 2021Applicant: Getzner Werkstoffe Holding GmbHInventor: Andreas AUGUSTIN
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Patent number: 11031699Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.Type: GrantFiled: February 9, 2018Date of Patent: June 8, 2021Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
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Patent number: 11018114Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.Type: GrantFiled: July 18, 2019Date of Patent: May 25, 2021Assignee: Intel IP CorporationInventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
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Publication number: 20210104359Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: ApplicationFiled: December 15, 2020Publication date: April 8, 2021Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Patent number: 10896780Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: GrantFiled: March 2, 2018Date of Patent: January 19, 2021Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Patent number: 10867934Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.Type: GrantFiled: March 27, 2018Date of Patent: December 15, 2020Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
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Publication number: 20200373259Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: ApplicationFiled: May 23, 2019Publication date: November 26, 2020Inventors: Sonja KOLLER, Kilian ROTH, Josef HAGN, Andreas WOLTER, Andreas AUGUSTIN
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Publication number: 20200365996Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Inventors: Kilian ROTH, Sonja KOLLER, Josef HAGN, Andreas WOLTER, Andreas AUGUSTIN