Patents by Inventor Andreas Grassmann
Andreas Grassmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162205Abstract: A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.Type: ApplicationFiled: November 10, 2023Publication date: May 16, 2024Applicant: Infineon Technologies Austria AGInventors: Marcus BÖHM, Stefan WÖTZEL, Andreas GRASSMANN, Bernd SCHMOELZER, Uwe SCHINDLER
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Publication number: 20240162129Abstract: A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: Christoph Bayer, Michael Fügl, Frank Singer, Thorsten Meyer, Fabian Craes, Andreas Grassmann, Frederik Otto
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Patent number: 11973012Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.Type: GrantFiled: July 26, 2021Date of Patent: April 30, 2024Assignee: Infineon Technologies Austria AGInventor: Andreas Grassmann
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Patent number: 11908760Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.Type: GrantFiled: January 13, 2022Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventor: Andreas Grassmann
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Patent number: 11862533Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.Type: GrantFiled: December 21, 2021Date of Patent: January 2, 2024Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Publication number: 20230361088Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.Type: ApplicationFiled: April 5, 2023Publication date: November 9, 2023Inventors: Ivan Nikitin, Thorsten Scharf, Marco Bäßler, Andreas Grassmann, Waldemar Jakobi
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Publication number: 20230361087Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.Type: ApplicationFiled: May 4, 2022Publication date: November 9, 2023Inventors: Ivan Nikitin, Thorsten Scharf, Marco Baessler, Andreas Grassmann, Waldemar Jakobi
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Publication number: 20230352378Abstract: A semiconductor package includes a substrate, a first and a second semiconductor die arranged on the substrate, a molded body encapsulating the first and second semiconductor dies, the molded body including a first external side facing away from the substrate, a plurality of electrical connectors extending at least partially through the molded body from the first external side to the first and/or second semiconductor die, and a plurality of plated conductive tracks arranged in trenches within the molded body on the first external side. T conductive tracks are coupled to the first and/or second semiconductor die by the electrical connectors.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Inventors: Andreas Grassmann, Ivan Nikitin
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Patent number: 11626351Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier.Type: GrantFiled: January 26, 2021Date of Patent: April 11, 2023Assignee: Infineon Technologies AGInventors: Ivan Nikitin, Timo Bohnenberger, Andreas Grassmann, Martin Mayer, Alexander Roth, Franz Zollner
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Patent number: 11598904Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.Type: GrantFiled: December 5, 2019Date of Patent: March 7, 2023Assignee: Infineon Technologies AGInventors: Ivan Nikitin, Dirk Ahlers, Andreas Grassmann, Andre Uhlemann
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Patent number: 11574889Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.Type: GrantFiled: June 4, 2013Date of Patent: February 7, 2023Assignee: Infineon Technologies AGInventors: Ottmar Geitner, Wolfram Hable, Andreas Grassmann, Frank Winter, Christian Neugirg, Ivan Nikitin
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Publication number: 20230035550Abstract: A semiconductor device module includes an application board, a plurality of semiconductor device packages disposed on the application board, each one of the semiconductor device packages including a semiconductor die, a leadframe including a plurality of leads, the leads including a spring support and a heat dissipation element, and an encapsulant embedding the semiconductor die and first portions of the leads, an external heatsink, and one or more thermally conductive interface layers disposed between the semiconductor device package and the heatsink.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Inventors: Andreas Grassmann, Edward Fuergut, Uwe Schindler
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Publication number: 20230025736Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.Type: ApplicationFiled: July 26, 2021Publication date: January 26, 2023Inventor: Andreas Grassmann
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Publication number: 20220285178Abstract: A device for forming a housing for a power semiconductor module arrangement includes a mold. The mold includes a first cavity including a plurality of first openings and a second opening, the second opening being coupled to a runner system, wherein the runner system is configured to inject a mold material into the first cavity through the second opening. The device further includes a plurality of sleeves or hollow bushings, wherein a first end of each of the plurality of sleeves or hollow bushings is arranged in one of the first openings, and wherein a second end of each of the plurality of sleeves or hollow bushings extends to the outside of the mold, a heating element configured to heat the mold, and a cooling element configured to cool the plurality of sleeves or hollow bushings.Type: ApplicationFiled: March 3, 2022Publication date: September 8, 2022Inventor: Andreas Grassmann
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Publication number: 20220238422Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrierType: ApplicationFiled: January 26, 2021Publication date: July 28, 2022Inventors: Ivan Nikitin, Timo Bohnenberger, Andreas Grassmann, Martin Mayer, Alexander Roth, Franz Zollner
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Publication number: 20220238413Abstract: A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate.Type: ApplicationFiled: January 22, 2021Publication date: July 28, 2022Applicant: Infineon Technologies AGInventor: Andreas GRASSMANN
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Publication number: 20220230930Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.Type: ApplicationFiled: January 13, 2022Publication date: July 21, 2022Applicant: Infineon Technologies AGInventor: Andreas GRASSMANN
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Publication number: 20220115293Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Patent number: 11264356Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.Type: GrantFiled: April 7, 2020Date of Patent: March 1, 2022Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf
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Patent number: 11244886Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.Type: GrantFiled: September 21, 2017Date of Patent: February 8, 2022Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass