Patents by Inventor Andreas Kerber
Andreas Kerber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133952Abstract: Methods and apparatus for a diagnostic in situ ring oscillator (RO) circuit for DC and transient characterization. The RO circuit includes a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, where each stage includes a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of a CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage. The first stage is a configurable enable stage to enable the inverter chain to be set into a defined logic state, followed by multiple pre-stage-DUT stages. The output of the last stage is feed back to the input of the enable stage to form an RO feedback signal. The RO circuit can operate in multiple modes including an AC mode, a DC mode, and a hybrid mode.Type: ApplicationFiled: December 26, 2023Publication date: April 25, 2024Inventors: Andreas KERBER, Phillip KLIZA
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Patent number: 10126354Abstract: CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.Type: GrantFiled: June 28, 2017Date of Patent: November 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Andreas Kerber, Tanya Nigam, Fernando Guarin
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Patent number: 10054630Abstract: At least one method and system involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.Type: GrantFiled: June 16, 2017Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Suresh Uppal, Andreas Kerber, William McMahon
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Publication number: 20170292986Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.Type: ApplicationFiled: June 16, 2017Publication date: October 12, 2017Applicant: GLOBALFOUNDRIES, INC.Inventors: Suresh Uppal, Andreas Kerber, William McMahon
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Patent number: 9702926Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.Type: GrantFiled: May 27, 2014Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Suresh Uppal, Andreas Kerber, William McMahon
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Patent number: 9599656Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.Type: GrantFiled: November 25, 2014Date of Patent: March 21, 2017Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Suresh Uppal, Andreas Kerber, William McMahon, Eduard A. Cartier
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Publication number: 20160204098Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.Type: ApplicationFiled: March 24, 2016Publication date: July 14, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Andreas Kerber, Suresh Uppal, Salvatore Cimino, Hao Jiang
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Publication number: 20160146879Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Applicants: GLOBAL FOUNDRIES INC., International Business Machines CorporationInventors: Suresh Uppal, Andreas Kerber, William McMahon, Eduard A. Cartier
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Patent number: 9324822Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.Type: GrantFiled: July 1, 2014Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Andreas Kerber, Suresh Uppal, Salvatore Cimino, Hao Jiang
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Publication number: 20160005828Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.Type: ApplicationFiled: July 1, 2014Publication date: January 7, 2016Inventors: Andreas Kerber, Suresh Uppal, Salvatore Cimino, Hao Jiang
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Publication number: 20150377956Abstract: A methodology for inline characterization and temperature profiling that enables parallel measurement of device characteristics at multiple temperatures and the resulting device are disclosed. Embodiments may include calibrating a first device under test (DUT) with respect to at least one heating structure in a metal layer of an integrated circuit (IC), applying a heater voltage to the at least one heating structure, and measuring at least one characteristic of the first DUT at a first temperature corresponding to the heater voltage.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: William MCMAHON, Andreas KERBER, Luigi PANTISANO, Suresh UPPAL
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Publication number: 20150346271Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Suresh Uppal, Andreas Kerber, William McMahon
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Patent number: 8817570Abstract: Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.Type: GrantFiled: February 13, 2012Date of Patent: August 26, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: William McMahon, Andreas Kerber, Tanya Nigam
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Patent number: 8778750Abstract: A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.Type: GrantFiled: May 5, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Eduard Albert Cartier, Michael P. Chudzik, Andreas Kerber, Siddarth Krishnan, Naim Moumen
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Publication number: 20140110772Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.Type: ApplicationFiled: November 8, 2013Publication date: April 24, 2014Applicant: Globalfoundries, Inc.Inventors: Andreas Kerber, Tanya Nigam, Dieter Lipp, Marc Herden
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Patent number: 8610188Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.Type: GrantFiled: September 15, 2011Date of Patent: December 17, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Andreas Kerber, Tanya Nigam, Dieter Lipp, Marc Herden
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Publication number: 20130292778Abstract: A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.Type: ApplicationFiled: May 5, 2012Publication date: November 7, 2013Applicant: International Business Machines CorporationInventors: Eduard Albert Cartier, Michael P. Chudzik, Andreas Kerber, Siddarth Krishnan, Naim Moumen
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Publication number: 20130208555Abstract: Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: William McMahon, Andreas Kerber, Tanya Nigam
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Publication number: 20130069131Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Inventors: Andreas Kerber, Tanya Nigam, Dieter Lipp, Marc Herden
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Publication number: 20130033285Abstract: In accordance with a exemplary embodiments, methods for performing reliability testing of a plurality of transistors formed on a substrate includes simultaneously stressing the plurality of transistors by applying a voltage potential from each of a plurality of voltage sources to respective drain contacts of a like plurality of row groups and to gate contacts of a like plurality of column groups for a time interval, while applying a reference potential to the substrate and source contacts of the plurality of transistors. After stressing the plurality of transistors for a time interval, the transistors are each measured individually to collect reliability data.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: William McMahon, Andreas Kerber, Tanya Nigam, Rudolph Dirk