Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

Abstract: The present application relates to novel substituted 5-fluoro-1H-pyrazolopyridines, to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases, and to their use for producing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: The present application relates to novel substituted 5-fluoro-1H-pyrazolopyridines, to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases, and to their use for producing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: The present application relates to novel 3-phenylpropionic acid derivatives which carry a branched or cyclic alkyl substituent in the 3-position, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of cardiovascular diseases.

Abstract: The present application relates to novel substituted piperidinyltetrahydroquinolines, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of diabetic microangiopathies, diabetic ulcers on the extremities, in particular for promoting wound healing of diabetic foot ulcers, diabetic heart failure, diabetic coronary microvascular heart disorders, peripheral and cardial vascular disorders, thromboembolic disorders and ischaemias, peripheral circulatory disturbances, Raynaud's phenomenon, CREST syndrome, microcirculatory disturbances, intermittent claudication, and peripheral and autonomous neuropathies.

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.

Abstract: The present application relates to novel substituted 5-fluoro-1H-pyrazolopyridines, to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases, and to their use for producing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: The present application relates to novel 3-phenylpropionic acid derivatives which carry a branched or cyclic alkyl substituent in the 3-position, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of cardiovascular diseases.

Abstract: A disposable absorbent article having a topsheet, a backsheet, an absorbent core disposed between the topsheet and the backsheet, and a fluid management layer disposed between the topsheet and the absorbent core is disclosed. The disposable absorbent article provides improved fluid acquisition, improved stain size control, and improved performance when wet.

Abstract: A disposable absorbent article having a topsheet, a backsheet, an absorbent core disposed between the topsheet and the backsheet, and a fluid management layer disposed between the topsheet and the absorbent core is disclosed. The fluid management layer is an integrated, carded, nonwoven disposed between the topsheet and the absorbent core. The absorbent article exhibits an average stain size of less than about 2400 mm{circumflex over (?)}2, when measured in accordance with the Stain Size test method.

Abstract: A fluid management layer having an integrated, carded nonwoven is described. The fluid management layer has a basis weight of between about 40 grams per square meter (gsm) and about 75 gsm; a plurality of absorbent fibers; a plurality of stiffening fibers; and a plurality of resilient fibers. The fluid management layer has a caliper factor of at least about 0.13.

Abstract: A fluid management layer having an integrated, carded nonwoven is described. The fluid management layer has a basis weight of between about 40 grams per square meter (gsm) and about 75 gsm, and a plurality of absorbent fibers, a plurality of stiffening fibers and a plurality of resilient fibers. The fluid management layer has a compression distance of at least 0.

Abstract: The present application relates to novel substituted 5-fluoro-1H-pyrazolopyridines, to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases, and to their use for producing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: The present application relates to novel substituted imidazo[1,2-a]pyridine-3-carboxamides of the general formula (I) to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases and to their use for preparing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.