Abstract: A solar cell includes a semiconductor substrate and an antireflection layer arranged on the light incidence side on the front-side surface of a semiconductor substrate. The antireflection layer has a limit voltage of less than 10 volts, less than 5 volts, or less than 3 volts, along a layer thickness of the antireflection layer.

Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Abstract: Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.

Abstract: Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to determine an operating point of an integrated circuit.

Abstract: Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

Abstract: In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Abstract: Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to determine an operating point of an integrated circuit.

Abstract: Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.

Abstract: In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Abstract: Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Abstract: A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

Abstract: A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed.

Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Abstract: A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

Abstract: A method, a memory device and a test unit to test such memory device is provided. The memory device comprises a memory cell array including a multitude of memory cells each having a variable characteristic. The method comprises identifying the characteristic of each memory cell and assigning memory cells of the multitude of memory cells to a weak group in dependence on the identified characteristic. Then the stored information of the memory cells assigned to the weak group is restored in order to modify the characteristics of these memory cells.

Abstract: An individual configuration contains at least a first structure and a second structure, which are aligned with respect to each other. A position sensing device that senses a relative position of the first structure with respect to the second structure, in order to establish that a manipulation has been performed on the configuration, is provided.

Abstract: The access time for the use of an electronic device, for example a chip, is prolonged after each unauthorized access attempt. The access time is determined by the time for the matching of the turn-on voltages of two floating gate cells. Before an access attempt, the turn-on voltage of one cell is set to a predefined initial value and the turn-on voltage of the other cell is set to a value which is higher in comparison and which is increased after each unauthorized access.

Abstract: A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and of which at least one contains functional components, includes the steps of providing respective conductor tracks in the part chips and providing feed-through contacts at the respective contact areas, which in each case interconnect conductor tracks of various part chips so that a continuous electrical signal path running through the part chips is formed. An electrical signal is transmitted from a transmitting device provided at a first end of the electrical signal path to a receiving device provided at a second end of the electrical signal path. When the electrical signal cannot be received, it is determined that the chip stack has been damaged. A device for securing a chip stack and a chip configuration are also provided.