Patents by Inventor Andreas Logisch
Andreas Logisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7426669Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.Type: GrantFiled: October 14, 2004Date of Patent: September 16, 2008Assignee: Infineon Technologies AGInventors: Björn Flach, Andreas Logisch, Wolfgang Ruf, Michael Schittenhelm, Martin Schnell
-
Patent number: 7414421Abstract: An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result.Type: GrantFiled: November 30, 2005Date of Patent: August 19, 2008Assignee: Infineon Technologies AGInventors: Björn Flach, Andreas Logisch, Monica De Castro Martins, Wolfgang Ruf, Martin Schnell
-
Patent number: 7360139Abstract: A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor component under production conditions. The specific semiconductor component includes measuring units that are connected to connection contacts and in each case provide the functionality of a signal generator, a signal detector, a digital communication interface and a receiving unit for trigger signals. The specific semiconductor component further includes a trigger logic to convey trigger signals between the receiving unit of a first one and the signal generator or detector of a second one of the measuring units.Type: GrantFiled: October 25, 2005Date of Patent: April 15, 2008Assignee: Infineon Technologies AGInventors: Andreas Logisch, Mónica De Castro Martins, Björn Flach, Wolfgang Ruf, Martin Schnell, Ana Leao
-
Publication number: 20060181300Abstract: A test apparatus comprises a receptacle unit for holding a circuit unit to be tested and for making contact with contact-making units of the circuit unit, a test system for generating input data to be applied to the circuit unit and for analysing output data generated by the circuit unit in response to the input data, a tester channel being comprised of a plurality of lines to electrically connect the test system to connection pins which are fitted in the receptacle unit and are intended to connect the circuit unit and to communicate the input data and the output data between the test system and the circuit unit, and a signal output unit for outputting verification signals when testing the circuit unit. The signal output unit is arranged in the receptacle unit between the circuit unit and the connection pins for connecting the circuit unit.Type: ApplicationFiled: February 2, 2006Publication date: August 17, 2006Inventors: Bjorn Flach, Andreas Logisch, Mehdi Rostami, Martin Schnell
-
Publication number: 20060156149Abstract: A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor component under production conditions. The specific semiconductor component includes measuring units that are connected to connection contacts and in each case provide the functionality of a signal generator, a signal detector, a digital communication interface and a receiving unit for trigger signals. The specific semiconductor component further includes a trigger logic to convey trigger signals between the receiving unit of a first one and the signal generator or detector of a second one of the measuring units.Type: ApplicationFiled: October 25, 2005Publication date: July 13, 2006Inventors: Andreas Logisch, Monica Martins, Bjorn Flach, Wolfgang Ruf, Martin Schnell, Ana Leao
-
Publication number: 20060149491Abstract: An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result.Type: ApplicationFiled: November 30, 2005Publication date: July 6, 2006Applicant: Infineon Technologies AGInventors: Bjorn Flach, Andreas Logisch, Monica De Castro Martins, Wolfgang Ruf, Martin Schnell
-
Publication number: 20060026480Abstract: Method for the generation of test signals (TS) by means of a test signal generator to a component (6) to be tested, the test signal generator generating rising and falling signal edges which are in each case assigned to successive time windows (TS1-TSN) with predetermined time durations (T0), having the following method steps of: determining a command sequence frequency (BAF) of the component (6) to be tested; allocating instants (TS1U, . . . TSNU) for rising signal edges and allocating instants (TS1D . . . TSND) for falling signal edges for the successive time windows (TS1-TSN), the instants for the rising or falling signal edges (TS1D, . . .Type: ApplicationFiled: July 22, 2005Publication date: February 2, 2006Inventor: Andreas Logisch
-
Publication number: 20050138491Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.Type: ApplicationFiled: October 14, 2004Publication date: June 23, 2005Applicant: Infineon Technologies AGInventors: Bjorn Flach, Andreas Logisch, Wolfgang Ruf, Michael Schittenhelm, Martin Schnell
-
Publication number: 20050055618Abstract: The invention provides a test arrangement for testing circuit units under test (101, 101a-101n) having a test apparatus for holding the circuit units under test (101, 101a-101n), input/output channels (DQ0-DQn) for connecting the circuit units under test (101, 101a-101n) to the test apparatus and for data interchange, and test mode output channels (103, 103a-103n) for outputting a test result signal (104, 104a-104n), where at least one diversion unit (102, 102a-102n) for connecting one of the test mode output channels (103, 103a-103n) to one of the input/output channels (DQ0-DQn) is provided in the circuit units under test (101, 101a-101n) so that the test result signal (104, 104a-104n) which is output from the circuit unit under test (101, 101a-101n) can be diverted from the circuit unit under test (101, 101a-101n) to a prescribable one of the input/output channels (DQ0-DQn).Type: ApplicationFiled: August 25, 2004Publication date: March 10, 2005Inventors: Thomas Finteis, Bjorn Flach, Klaus Hoffman, Andreas Logisch, Wolfgang Ruf, Martin Schnell
-
Patent number: 6777924Abstract: A method and device allow testing functionally identical semiconductor devices on a programmable testing device. The semiconductor devices are placed in magazine devices and a uniform magazine interface with respect to the testing device is provided for similar semiconductor devices in different types of packages. The semiconductor devices are advantageously tested one after the other on a testing device essentially without deference to their type of package and without any mechanical conversions being necessary on the testing device.Type: GrantFiled: February 28, 2003Date of Patent: August 17, 2004Assignee: Infineon Technologies AGInventors: Björn Flach, Wolfgang Ruf, Martin Schnell, Jörg Stippler, Andreas Logisch
-
Patent number: 6759854Abstract: A test apparatus comprises an input for receiving a test signal from a test signal source, wherein a signal line with a predefined characteristic wave impedance can be connected to the input. The test apparatus further comprises branching means with a first and a plurality of second terminals, the first terminal being connected to the input. The test apparatus further comprises a plurality of distribution lines, wherein each distribution line is connected to one of the plurality of second terminals of branching means, wherein one of the devices under test can be connected to each distribution line at the output side, each distribution line having a characteristic wave impedance, which is substantially equal to the product of the predefined characteristic wave impedance of the signal line and the number of distribution lines. Thus, a signal matching is given at the branching point, so that no amplitude or signal rise time distortions of the excitation signals occur at the inputs of the devices under test.Type: GrantFiled: July 30, 2002Date of Patent: July 6, 2004Assignee: Infineon TechnologiesInventor: Andreas Logisch
-
Publication number: 20030173950Abstract: A method and device allow testing functionally identical semiconductor devices on a programmable testing device. The semiconductor devices are placed in magazine devices and a uniform magazine interface with respect to the testing device is provided for similar semiconductor devices in different types of packages. The semiconductor devices are advantageously tested one after the other on a testing device essentially without deference to their type of package and without any mechanical conversions being necessary on the testing device.Type: ApplicationFiled: February 28, 2003Publication date: September 18, 2003Inventors: Bjorn Flach, Wolfgang Ruf, Martin Schnell, Jorg Stippler, Andreas Logisch
-
Publication number: 20030030427Abstract: A test apparatus comprises an input for receiving a test signal from a test signal source, wherein a signal line with a predefined characteristic wave impedance can be connected to the input. The test apparatus further comprises branching means with a first and a plurality of second terminals, the first terminal being connected to the input. The test apparatus further comprises a plurality of distribution lines, wherein each distribution line is connected to one of the plurality of second terminals of branching means, wherein one of the devices under test can be connected to each distribution line at the output side, each distribution line having a characteristic wave impedance, which is substantially equal to the product of the predefined characteristic wave impedance of the signal line and the number of distribution lines. Thus, a signal matching is given at the branching point, so that no amplitude or signal rise time distortions of the excitation signals occur at the inputs of the devices under test.Type: ApplicationFiled: July 30, 2002Publication date: February 13, 2003Inventor: Andreas Logisch